// 3-2-2022
// master output from suggested workaround where the slave does the following:
// point the transaction txBuf to the second element
// call SSIDataPut(SSI0_BASE, (uint32_t) slaveTxBuffer[0]) prior to SPI_transfer() with the first element
//
// The workaround works for the first transfer but then subsequent transfers have an additional 0x00 
// added to the front of the slave's transmission.

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99 0x00

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88 0x99

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x77 0x88

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x00 0x00 0x11 0x22 0x33 0x44 0x55 0x66 0x77

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x00 0x00 0x00 0x11 0x22 0x33 0x44 0x55 0x66

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x00 0x00 0x00 0x00 0x11 0x22 0x33 0x44 0x55

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x00 0x00 0x00 0x00 0x00 0x11 0x22 0x33 0x44

Set MRDY to low
Wait for SRDY interrupt (falling edge)
Set MRDY to high
masterRxBuffer: 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x11 0x22 0x33