The following sequence should be used to initilaize SRC4392.

1. Apply power and external reset.

2. Write all control registers on Page 0 except register 0x01.

3. Apply MCLK, as well as any audio clocks desired for Ports A and B.

4. Write register 0x01 on Page 0 to power up the desired blocks.

5. Disable DIT buffer transfers by setting the TXBTD bit in register 0x08, Page 0, to a 1.

6. Write 0x02 to register 0x7F to set Page 2 as the active page.

7. Write data to the DIT C and U buffers on Page 2 as desired.

8. Write 0x00 to address 0x7F to set Page 0 as the active page.

9. Enable DIT buffer transfers by setting the TXBTD bit in register 0x08, Page 0, to a 0. 
This will update the DIT TA buffer with the data written to Page 2 registers.

Example for Implementation of above:

1. External reset

2. Setting control registers on page 0 (it's always register address first, then data [all values in hex])

  w e0  7f 00      //Set Register Page 0
  w e0  03 20      // I²S Port A: Clock Slave, 24 Bit Audio MSB, Output Signal from Receiver - NOT from SRC
  w e0  04 00      // I²S  Port A: MCLK Source = MCLK; MCLK Freq = 128x LRCLK (MCLK Freq other than 128x just for Master Mode operation)
  w e0  07 00      // Clock Start Output; Transmitter MCLK Divider == FPGA CLK / 128
  w e0  09 01      // Transmitter Channel State Update via SPI
  w e0  0d 00      // Receiver Input == RX1, Ref CLK RXCKI (ext.)
  w e0  0E 00      // Receiver Mute if No CLK, Superclock on ext. Pin, CLK Divider = 4
       // Receiver PLL Ref Clk according Data Sheet (Table 4, S.60)
  w e0  0F 22   
  w e0  10 00    
  w e0  11 00  
       //
  w e0  2D 02      // SRC Source == Receiver, ref. CLK FPGA

3. Enable clock  (mclk, frame sync, sample clock)

4.  w e0  01 37  // switch on SRC, Receiver, Transmitter, I²S Port A


Here is the script for steps 5 to 9:


w e0 08 08 // disable the DIT buffer transfer

w e0 7f 02 // set page to 2

w e0 2e ee // write ee to reg 2e on page 2

w e0 2f ff //write ff to reg 2f on page 2

w e0 7f 00 //change the page back to 0

w e0 08 00 // enable the DIT buffer transfer

w e0 7f 02 // switch back to page 2

r e0 2e 01 // read back reg 2e on page 2

r e0 2f 01 // read back reg 2f on page 2

w e0 7f 00 // set page to page 0