###############################################
#
# For use with the following firmware image:
# ..\image\USBMODEVM0200_48KHZ.BIN
#
# This script configures both ADC and DAC
# channels for line-in and headphone
# monitoring.
#
# An analog loopback test can be performed by
# connecting a 1/8" male to male cable from
# J10 (Headphone Test) to J1 (IN1).
#
###############################################



###############################################
# Software Reset
###############################################
#
# Select Page 0
w 30 00 00
#
# Initialize the device through software reset
w 30 01 01
#
###############################################



###############################################
# Clock and Interface Settings
# ---------------------------------------------
# The codec receives: MCLK = 12.288 MHz,
# BLCK = 3.072 MHz, WCLK = 48 kHz
###############################################
#
# Select Page 0
w 30 00 00
#
# PLL_clkin = MCLK, codec_clkin = PLL_CLK,
# PLL on, P=1, R=1, J=8, D=0000
w 30 04 03 91 08 00 00
#
# NDAC = 2, MDAC = 8, dividers powered on
w 30 0b 82 88
#
# DOSR = 128
w 30 0D 00 80
#
# NADC = 2, MADC = 8, dividers powered on
w 30 12 82 88
#
# AOSR = 128
w 30 14 80
#
###############################################



###############################################
# Configure Power Supplies
###############################################
#
# Select Page 1
w 30 00 01
#
# Power up AVDD LDO
w 30 02 A9
#
# Disable weak AVDD in presence of external
# AVDD supply
w 30 01 08
#
# Enable Master Analog Power Control
# Power up AVDD LDO
w 30 02 A1
#
# Set the input power-up time to 3.1ms (for ADC)
w 30 47 32
#
# Set the REF charging time to 40ms
w 30 7b 01
#
###############################################



###############################################
# Configure Processing Blocks
###############################################
#
# Select Page 0
w 30 00 00
#
# PRB_P2 and PRB_R2 selected
w 30 3C 02 02
#
###############################################



###############################################
# Configure ADC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# Route IN2L to LEFT_P with 20K input impedance
w 30 34 20
#
# Route CM1L to LEFT_M with 20K input impedance
w 30 36 80
#
# Route IN2R to RIGHT_P with 20K input impedance
w 30 37 20
#
# Route CM1R to RIGHT_M with 20K input impedance
w 30 39 80
#
# Unmute Left MICPGA, Gain selection of 6dB to
# make channel gain 0dB, since 20K input
# impedance is used single ended
w 30 3b 0c
#
# Unmute Right MICPGA, Gain selection of 6dB to
# make channel gain 0dB, since 20K input
# impedance is used single ended
w 30 3c 0c
#
# Select Page 0
w 30 00 00
#
# Power up LADC/RADC
w 30 51 c0
#
# Unmute LADC/RADC
w 30 52 00
#
###############################################



###############################################
# Configure DAC Channel
###############################################
#
# Select Page 1
w 30 00 01
#
# De-pop: 5 time constants, 6k resistance
w 30 14 25
#
# Route LDAC/RDAC to HPL/HPR
w 30 0c 08 08
#
# Power up HPL/HPR
w 30 09 30
#
# Unmute HPL/HPR driver, 0dB Gain
w 30 10 00 00
#
# Select Page 0
w 30 00 00
#
# DAC => 0dB
w 30 41 00 00
#
# Power up LDAC/RDAC
w 30 3f d6
#
# Unmute LDAC/RDAC
w 30 40 00
#
###############################################