# Page 0
w 30 00 00
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# Software Reset
w 30 01 01
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# Page 0
w 30 00 00
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# NDAC/MDAC powered up; NDAC = 1; MDAC = 2
w 30 0B 81 82
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# NADC/MADC powered up; NADC = 1; MADC = 2
w 30 12 81 82
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# Page 0
w 30 00 00
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# DAC Signal Processing Block PRB_P1
w 30 3C 01
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# ADC Signal Processing Block PRB_R1
w 30 3D 01
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# Page 1
w 30 00 01
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# Disabled weak connection of AVDD with DVDD
w 30 01 08
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# Analog Blocks Enabled
w 30 02 00
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# Analog inputs power up time is 6.4ms
w 30 47 32
#
# Reference will power up in 40ms when analog blocks are powered up
w 30 7B 01
#
# Page 1
w 30 00 01
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# MICBIAS powered up; MICBIAS = 2.075V or 2.5V
w 30 33 60
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# IN3L is routed to Left MICPGA with 10k resistence
w 30 34 04
#
# CM is routed to Left MICPGA via CM1L to 10k resistence
w 30 36 40
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# Left MICPGA Gain is enabled; Volume control = 0.0dB
w 30 3B 00
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# Page 0 
w 30 00 00
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# Left Channel ADC is powered up
w 30 51 80
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# Left ADC Channel Un-Muted
w 30 52 08
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# Page 1
w 30 00 01
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# Headphone ramps determined with 6k; Headphone ramp power up 
# in 5 time constants
w 30 14 25
#
# Left/Right channel DAC reconstruction filter's positive
# terminal routed to HPL/HPR
w 30 0C 08 08
#
# HPL/HPR is powered up
w 30 09 30
#
# HPL/HPR is not muted (0dB)
w 30 10 00 00
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# Page 0
w 30 00 00
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# Left/Right DAC volume = 0dB
w 30 41 00 00
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# Left/Right DAC powered up; Left/Right DAC to Left/Right Channel
# Soft-Stepping is disabled
w 30 3F D6
#
# Left/Right DAC not muted
w 30 40 00
#
# Page 0
w 30 00 00
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# Headset Detection Enabled
w 30 43 80