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# ADC Stereo Record - High Performance
# SE input signal from IN1L/IN1R
# AVDDx_18, HVDD_18, CPVDD_18 = 1.8V; IOVDD, AVDD3_33, RECVDD_33 = 3.3V; SLVDD, SRVDD, SPK_V = 5V, DVdd = 1.8V
# MCLK = 12.288, Fs = 48kHz
# PLL Disabled, AOSR = 128, PTM_R1
# CM = 0.9V
# Primary I2S Interface used with WCLK & BCLK as inputs to the device
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# Software Reset
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w 30 00 00        # Initialize to Page 0
w 30 7f 00        # Initialize to Book 0
w 30 01 01        # Initialize the device through software reset
d 1               # Delay 1 millisecond

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# Power and Analog Configuration
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w 30 00 01        # Select Page 1
w 30 01 00        # Disable weak AVDD to DVDD connection and make analog supplies available
w 30 7a 01        # REF charging time = 40ms
w 30 79 33        # Set the quick charge of input coupling cap for analog inputs

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# Clock configuration
# MCLK = 12.288 MHz, BCLK = 3.072 MHz, WCLK = 48 kHz (slave)
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w 30 00 00        # Select Page 0
w 30 04 00        # Set ADC_CLKIN as MCLK1 -- default not mandatory to program
w 30 12 81        # Power Up NADC, NADC = 1
w 30 13 82        # Power Up MADC, MADC = 2
w 30 14 80        # Program the OSR of ADC to 128, ADC_FS = ADC_MOD_CLK / AOSR = 6.144MHz / 128 = 48kHz

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# Audio Serial Interface Routing Configuration - Audio Serial Interface #2
# ASI #2 recording
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w 30 00 04        # Select Page 4
w 30 11 00        # Audio Serial Interface #2 is set to I2S mode, 16-bit

w 30 1a 24         # Route ASI#2 WCLK as output to WCLK2 and BCLK as output to BCLK2

w 30 17 01 # Route ADC data to Audio Serial Interface #2
w 30 18 50 # ASI#2 Left Channel data sent to Left Channel DAC, ASI#2 Right channel data sent to Right Channel DAC
w 30 45 04 # Select WCLK2 pin as WCLK for Audio Serial Interface #2
w 30 46 04 # Select BCLK2 pin as BCLK for Audio Serial Interface #2
w 30 47 22 # Select DOUT2 pin as DOUT for Audio Serial Interface #2
w 30 48 20 # Select DIN2 pin as DIN for Audio Serial Interface #2
w 30 76 16 # Only ASI#2 Routed to DAC miniDSP Data Input 1


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# Signal Processing Settings 
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w 30 00 00        # Select Page 0
w 30 3d 01        # Set the ADC PRB Mode to PRB_R1

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# ADC Input Channel Configuration --- IN1L / IN1R
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w 30 00 01        # Select Page 1

# IF two SINGLE ENDED INPUTS: 
w 30 08 00        # Set the input common mode to 0.9V
w 30 34 80        # Route IN1L to LEFT ADCPGA with 20K input impedance
w 30 36 80	  # Route CM1 to left PGA with 20k input impedance
w 30 37 80        # Route IN1R to RIGHT ADCPGA with 20K input impedance
w 30 39 80	  # CM1 to Right PGA M terminal, 20k input impedance

# IF DIFFERENTIAL (must be on RIGHT PGA ONLY for IN1)
#w 30 37 80 	# set IN1R to right PGA P terminal, 20k input impedance
#w 30 39 20 	# set IN1L to right PGA L terminal, 20k input impedance


w 30 3B 00        # Left Channel Analog ADC PGA = 0 dB
w 30 3C 00        # Right Channel Analog ADC PGA = 0 dB
w 30 3D 00        # ADC Analog programmed for PTM_R4

w 30 00 00        # Select Page 0
w 30 51 C0        # Power-up ADC Channels, left and right
w 30 52 00        # Unmute ADC channel and Fine Gain = 0dB