// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
 * Copyright 2020 Technexion Ltd.
 *
 * Author: Richard Hu <richard.hu@technexion.com>
 *
 */

/dts-v1/;

#include <dt-bindings/usb/pd.h>
#include "imx8mm.dtsi"

/ {
	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		rpmsg_reserved: rpmsg@0xb8000000 {
			no-map;
			reg = <0 0xb8000000 0 0x400000>;
		};
	};

	chosen {
		stdout-path = &uart2;
	};

	bt_reg_on: btreg_on {
		compatible = "gpio-reset";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_bt_ctrl>;
		reset-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
		reset-delay-us = <2000>;
		reset-post-delay-ms = <40>;
		#reset-cells = <0>;
	};

	pcie0_refclk: pcie0-refclk {
		compatible = "fixed-clock";
		#clock-cells = <0>;
		clock-frequency = <100000000>;
	};

sound-tlv320aic31xx {
             compatible = "simple-audio-card";
             simple-audio-card,name = "tlv320aic31xx-codec";
             simple-audio-card,format = "i2s";
             simple-audio-card,frame-master = <&cpudai2>;
             simple-audio-card,bitclock-master = <&cpudai2>;
             /*simple-audio-card,mclk-fs=<256>;*/
             simple-audio-card,widgets =
                     "Headphone", "Headphone Jack";
             simple-audio-card,routing =
                     "Headphone Jack", "HPL",
                     "Headphone Jack", "HPR";

             cpudai2:simple-audio-card,cpu {
                     sound-dai = <&sai2>;
             };

             simple-audio-card,codec {
                     sound-dai = <&tlv320aic31xx>;
                     //system-clock-frequency = <24000000>;
                     clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
             };
        };

        clocks {
                codec_osc: aud_mclk {
                        compatible = "fixed-clock";
                        #clock-cells = <0>;
                        clock-frequency = <24000000>;
                        clock-output-names = "codec-mclk";
                };
        };
 
        reg_1p8v: regulator-1p8v {
                compatible = "regulator-fixed";
                regulator-name = "1P8V";
                regulator-min-microvolt = <1800000>;
                regulator-max-microvolt = <1800000>;
                regulator-always-on;
        };

        reg_3p3v: regulator-3p3v {
                compatible = "regulator-fixed";
                regulator-name = "3P3V";
                regulator-min-microvolt = <3300000>;
                regulator-max-microvolt = <3300000>;
                regulator-always-on;
        };

        reg_5v: regulator-5v {
                compatible = "regulator-fixed";
                regulator-name = "5V";
                regulator-min-microvolt = <5000000>;
                regulator-max-microvolt = <5000000>;
                regulator-always-on;
        };

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		wl_reg_on: wlreg_on {
			compatible = "regulator-fixed";
			pinctrl-names = "default";
			pinctrl-0 = <&pinctrl_wifi_ctrl>;
			regulator-name = "WL_REG_ON";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
			off-on-delay = <20000>;
			startup-delay-us = <100>;
			enable-active-high;
		};
	};
};

&A53_0 {
	cpu-supply = <&buck2_reg>;
};

&fec1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	phy-mode = "rgmii-id";
	phy-handle = <&ethphy0>;
	fsl,magic-packet;
	status = "okay";

	mdio {
		#address-cells = <1>;
		#size-cells = <0>;

		ethphy0: ethernet-phy@0 {
			compatible = "ethernet-phy-ieee802.3-c22";
			reg = <1>;
			at803x,led-act-blind-workaround;
			at803x,eee-disabled;
			rtl821x,aldps-disable;
			rtl821x,clkout-disable;
		};
	};
};

&pcie0{
	clocks = <&clk IMX8MM_CLK_PCIE1_ROOT>,
		 <&clk IMX8MM_CLK_PCIE1_AUX>,
		 <&clk IMX8MM_CLK_PCIE1_PHY>,
		 <&pcie0_refclk>;
	clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus";
	ext_osc = <0>;
	reserved-region = <&rpmsg_reserved>;
	status = "disabled";
};
&sai3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai3>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI3>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <24576000>;
	status = "disabled";
};

&sai2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	/*assigned-clocks = <&clk IMX8MM_CLK_SAI2>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	//assigned-clock-rates = <24576000>;
	assigned-clock-rates = <24000000>;*/
        clocks = <&clk IMX8MM_CLK_SAI2_IPG>,
                                         <&clk IMX8MM_CLK_DUMMY>,
                                         <&clk IMX8MM_CLK_SAI2_ROOT>,
                                         <&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_CLK_DUMMY>;
        clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3";
	status = "okay";
};

&sai1 {
	pinctrl-names = "default", "dsd";
	pinctrl-0 = <&pinctrl_sai1>;
	assigned-clocks = <&clk IMX8MM_CLK_SAI1>;
	assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
	assigned-clock-rates = <49152000>;
	clocks = <&clk IMX8MM_CLK_SAI1_IPG>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_SAI1_ROOT>, <&clk IMX8MM_CLK_DUMMY>,
		<&clk IMX8MM_CLK_DUMMY>, <&clk IMX8MM_AUDIO_PLL1_OUT>,
		<&clk IMX8MM_AUDIO_PLL2_OUT>;
	clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k";
	status = "disabled";
};

&uart1 { /* BT */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	assigned-clocks = <&clk IMX8MM_CLK_UART1>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	resets = <&bt_reg_on>;
	status = "okay";
};

&uart2 { /* console */
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
	status = "okay";
};

&uart3 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart3>;
	assigned-clocks = <&clk IMX8MM_CLK_UART3>;
	assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>;
	fsl,uart-has-rtscts;
	status = "okay";
};

&usbotg1 {
	dr_mode = "otg";
	hnp-disable;
	srp-disable;
	adp-disable;
	picophy,pre-emp-curr-control = <3>;
	picophy,dc-vol-level-adjust = <7>;
	status = "okay";
};

&usbotg2 {
	dr_mode = "host";
	picophy,pre-emp-curr-control = <3>;
	picophy,dc-vol-level-adjust = <7>;
	status = "okay";
};

/* WIFI SDIO */
&usdhc1 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc1>;
	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
	bus-width = <4>;
	no-1-8-v;
	vmmc-supply = <&wl_reg_on>;
	pm-ignore-notify;
	keep-power-in-suspend;
	non-removable;
	status = "okay";
};

/* SD card on CLIX connector */
&usdhc2 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
	cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>;
	bus-width = <4>;
	status = "okay";
};

/* eMMC on SOM */
&usdhc3 {
	pinctrl-names = "default", "state_100mhz", "state_200mhz";
	pinctrl-0 = <&pinctrl_usdhc3>;
	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
	bus-width = <8>;
	non-removable;
	status = "okay";
};

&wdog1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_wdog>;
	fsl,ext-reset-output;
	status = "okay";
};

&ecspi2 {
	#address-cells = <1>;
	#size-cells = <0>;
	num-cs = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_ecspi2 &pinctrl_ecspi2_cs>;
	cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>;
	status = "disabled";
};

&i2c1 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c1>;
	status = "okay";

	pmic@4b {
		compatible = "rohm,bd71847";
		reg = <0x4b>;
		pinctrl-0 = <&pinctrl_pmic>;
		interrupt-parent = <&gpio1>;
		interrupts = <3 GPIO_ACTIVE_LOW>;
		rohm,reset-snvs-powered;

		regulators {
			buck1_reg: BUCK1 {
				regulator-name = "BUCK1";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
			};

			buck2_reg: BUCK2 {
				regulator-name = "BUCK2";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1300000>;
				regulator-boot-on;
				regulator-always-on;
				regulator-ramp-delay = <1250>;
				rohm,dvs-run-voltage = <1000000>;
				rohm,dvs-idle-voltage = <900000>;
			};

			buck3_reg: BUCK3 {
				// BUCK5 in datasheet
				regulator-name = "BUCK3";
				regulator-min-microvolt = <700000>;
				regulator-max-microvolt = <1350000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck4_reg: BUCK4 {
				// BUCK6 in datasheet
				regulator-name = "BUCK4";
				regulator-min-microvolt = <3000000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck5_reg: BUCK5 {
				// BUCK7 in datasheet
				regulator-name = "BUCK5";
				regulator-min-microvolt = <1605000>;
				regulator-max-microvolt = <1995000>;
				regulator-boot-on;
				regulator-always-on;
			};

			buck6_reg: BUCK6 {
				// BUCK8 in datasheet
				regulator-name = "BUCK6";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <1400000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo1_reg: LDO1 {
				regulator-name = "LDO1";
				regulator-min-microvolt = <1600000>;
				regulator-max-microvolt = <1900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo2_reg: LDO2 {
				regulator-name = "LDO2";
				regulator-min-microvolt = <800000>;
				regulator-max-microvolt = <900000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo3_reg: LDO3 {
				regulator-name = "LDO3";
				regulator-min-microvolt = <1800000>;
				regulator-max-microvolt = <3300000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo4_reg: LDO4 {
				regulator-name = "LDO4";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};

			ldo6_reg: LDO6 {
				regulator-name = "LDO6";
				regulator-min-microvolt = <900000>;
				regulator-max-microvolt = <1800000>;
				regulator-boot-on;
				regulator-always-on;
			};
		};
	};
};

&i2c2 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c2>;
	status = "okay";
tlv320aic31xx:codec@18 {
                compatible = "ti,tlv320aic3100";
                reg = <0x18>;
                #sound-dai-cells = <0>;
                /* Regulators */
                AVDD-supply = <&reg_3p3v>;
                HPVDD-supply = <&reg_3p3v>;
                SPRVDD-supply = <&reg_5v>;
                SPLVDD-supply = <&reg_5v>;
                DVDD-supply = <&reg_1p8v>;
                IOVDD-supply = <&reg_1p8v>;
                /*clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
                clock-names = "mclk";
                assigned-clocks = <&clk IMX8MM_CLK_SAI2_ROOT>;
                assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>;
                assigned-clock-rates = <24000000>;*/
                ai31xx-micbias-vg = <1>;
        };

};

&i2c3 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c3>;
	status = "okay";
};

&snvs_rtc {
	status = "disabled";
};

&iomuxc {
	pinctrl-names = "default";

	pinctrl_fec1: fec1grp {
		fsl,pins = <
			MX8MM_IOMUXC_ENET_MDC_ENET1_MDC			0x3
			MX8MM_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
			MX8MM_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
			MX8MM_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
			MX8MM_IOMUXC_SD1_RESET_B_GPIO2_IO10	0x36	/* ENET_nRST */
		>;
	};

	pinctrl_i2c1: i2c1grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL			0x400001c3
			MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA			0x400001c3
		>;
	};

	pinctrl_i2c2: i2c2grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL			0x400001c3
			MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA			0x400001c3
		>;
	};

	pinctrl_i2c3: i2c3grp {
		fsl,pins = <
			MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL			0x400001c3
			MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA			0x400001c3
		>;
	};

	pinctrl_pmic: pmicirq {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO03_GPIO1_IO3		0x41
		>;
	};

	pinctrl_sai2: sai2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC	0xd6
			MX8MM_IOMUXC_SAI2_TXC_SAI2_TX_BCLK	0xd6
			MX8MM_IOMUXC_SAI2_MCLK_SAI2_MCLK	0xd6
			MX8MM_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0	0xd6
			MX8MM_IOMUXC_SAI2_RXD0_SAI2_RX_DATA0	0xd6
		>;
	};

	pinctrl_sai3: sai3grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI3_TXFS_SAI3_TX_SYNC	0xd6
			MX8MM_IOMUXC_SAI3_TXC_SAI3_TX_BCLK	0xd6
			MX8MM_IOMUXC_SAI3_TXD_SAI3_TX_DATA0	0xd6
			MX8MM_IOMUXC_SAI3_RXD_SAI3_RX_DATA0	0xd6
		>;
	};

	/* Bluetooth audio */
	pinctrl_sai1: sai1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC	0xd6
			MX8MM_IOMUXC_SAI1_TXC_SAI1_TX_BCLK	0xd6
			MX8MM_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0	0xd6
			MX8MM_IOMUXC_SAI1_RXD0_SAI5_RX_DATA0    0xd6
		>;
	};

	pinctrl_uart1: uart1grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
			MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
			MX8MM_IOMUXC_UART3_RXD_UART1_DCE_CTS_B	0x140
			MX8MM_IOMUXC_UART3_TXD_UART1_DCE_RTS_B	0x140
		>;
	};

	pinctrl_uart2: uart2grp {
		fsl,pins = <
			MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX	0x140
			MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX	0x140
		>;
	};

	pinctrl_uart3: uart3grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI1_SCLK_UART3_DCE_RX		0x140
			MX8MM_IOMUXC_ECSPI1_MOSI_UART3_DCE_TX		0x140
			MX8MM_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B		0x140
			MX8MM_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B	0x140
		>;
	};

	pinctrl_usdhc1: usdhc1grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
		>;
	};

	pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
		>;
	};

	pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
			MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
			MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
			MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
			MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
			MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
		>;
	};

	pinctrl_usdhc2_gpio: usdhc2grpgpio {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12	0x1c4
		>;
	};

	pinctrl_usdhc2: usdhc2grp {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
			MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
			MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
			MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
			MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
			MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
			MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
		>;
	};

	pinctrl_usdhc3: usdhc3grp {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x190
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d0
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d0
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d0
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d0
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d0
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d0
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d0
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d0
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d0
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x190
		>;
	};

	pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x194
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d4
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d4
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d4
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d4
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d4
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d4
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d4
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d4
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d4
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x194
		>;
	};

	pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
		fsl,pins = <
			MX8MM_IOMUXC_NAND_WE_B_USDHC3_CLK		0x196
			MX8MM_IOMUXC_NAND_WP_B_USDHC3_CMD		0x1d6
			MX8MM_IOMUXC_NAND_DATA04_USDHC3_DATA0		0x1d6
			MX8MM_IOMUXC_NAND_DATA05_USDHC3_DATA1		0x1d6
			MX8MM_IOMUXC_NAND_DATA06_USDHC3_DATA2		0x1d6
			MX8MM_IOMUXC_NAND_DATA07_USDHC3_DATA3		0x1d6
			MX8MM_IOMUXC_NAND_RE_B_USDHC3_DATA4		0x1d6
			MX8MM_IOMUXC_NAND_CE2_B_USDHC3_DATA5		0x1d6
			MX8MM_IOMUXC_NAND_CE3_B_USDHC3_DATA6		0x1d6
			MX8MM_IOMUXC_NAND_CLE_USDHC3_DATA7		0x1d6
			MX8MM_IOMUXC_NAND_CE1_B_USDHC3_STROBE 		0x196
		>;
	};

	pinctrl_wdog: wdoggrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0xc6
		>;
	};

	pinctrl_wifi_ctrl: wifi_ctrlgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x41 /* WL_REG_ON */
		>;
	};

	pinctrl_bt_ctrl: bt_ctrlgrp {
		fsl,pins = <
			MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12	0x41 /* BT_REG_ON */
		>;
	};

	pinctrl_ecspi2: ecspi2grp {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK	0x82
			MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI	0x82
			MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO	0x82
		>;
	};

	pinctrl_ecspi2_cs: ecspi2cs {
		fsl,pins = <
			MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13	0x16
		>;
	};
};

&lcdif {
	status = "okay";
};

&vpu_g1 {
	status = "okay";
};

&vpu_g2 {
	status = "okay";
};

&vpu_h1 {
	status = "okay";
};

&gpu {
	status = "okay";
};