printk("Codec to init the Playback.\n");
	// Software Reset
	aic3268_write(codec, PAGE_0 + 0x00, 0x00);  		
	aic3268_write(codec, PAGE_0 + 0x7F, 0x00);  		
	aic3268_write(codec, PAGE_0 + 0x01, 0x01);  		

	mdelay(1);

	// Clock configuration
	aic3268_write(codec, PAGE_0 + 0x04, 0x00);  	
	aic3268_write(codec, PAGE_0 + 0x0B, 0x81);  		
	aic3268_write(codec, PAGE_0 + 0x0C, 0x82);  		
	aic3268_write(codec, PAGE_0 + 0x0D, 0x00);  		
	aic3268_write(codec, PAGE_0 + 0x0E, 0x80);  		
	
	// Initialize the Codec
	aic3268_write(codec, PAGE_1 + 0x01, 0x00);  		
	aic3268_write(codec, PAGE_1 + 0x7A, 0x01);  		
	
	// ASI #1 configuration
	aic3268_write(codec, PAGE_4 + 0x01, 0x00);  		
	aic3268_write(codec, PAGE_4 + 0x0A, 0x00);  		

	// Signal processing
	aic3268_write(codec, PAGE_0 + 0x3C, 0x01);  		

	// DAC configuration
	aic3268_write(codec, PAGE_1 + 0x03, 0x00);  		
	aic3268_write(codec, PAGE_1 + 0x04, 0x00);  		
	aic3268_write(codec, PAGE_1 + 0x16, 0x82);  		
	// Power up the Left and Right DAC Channels
	aic3268_write(codec, PAGE_0 + 0x3F, 0x80); 

	// unMute the DAC digital volume control
	aic3268_write(codec, PAGE_0 + 0x40, 0x04);

		
		printk("Codec to init the Capture.\n");
		// Power up NADC,MADC and set NADC = 1,MADC = 2
		aic3268_write(codec, PAGE_0 + 0x12, 0x81);  		
		aic3268_write(codec, PAGE_0 + 0x13, 0x81);  		
		// Set AOSR = 128
		aic3268_write(codec, PAGE_0 + 0x14, 0x80);  		
		// Disable the weak connection beween AVDD and DVDD
		aic3268_write(codec, PAGE_1 + 0x01, 0x00);  		
		// set the REF charging time to 40 ms
		aic3268_write(codec, PAGE_1 + 0x7A, 0x01);
		// set the quick charge of imput coupling cap for analog inputs
		aic3268_write(codec, PAGE_1 + 0x79, 0x33);
		// ASI#1 confiuration
		// set ASI#1 16bits,I2S mode
		aic3268_write(codec, PAGE_4 + 0x01, 0x00);
		aic3268_write(codec, PAGE_4 + 0x0A, 0x00);
	
		//Set the ADC PRB Mode to PRB_R1
		aic3268_write(codec, PAGE_0 + 0x3D, 0x01);

		// ADC configuration
		// Mic Bias enabled,Source = Avdd,1.62V
		aic3268_write(codec, PAGE_1 + 0x33, 0x44);
		// Route IN4L and IN4R to LEFT ADCPGA with 20K input impedance
		aic3268_write(codec, PAGE_1 + 0x35, 0x30);
		// Route IN4L and IN4R to RIGHT ADCPGA with 20K input impedance
		//aic3268_write(codec, PAGE_1 + 0x38, 0x30);

		// Left Channel Analog ADC PGA = 30 dB
		aic3268_write(codec, PAGE_1 + 0x3B, 0x00);
		// Right Channel Analog ADC PGA = 30 dB
		//aic3268_write(codec, PAGE_1 + 0x3C, 0x3C);
	
		// Left Channel Analog ADC Volume = -8 dB
		aic3268_write(codec, PAGE_0 + 0x53, 0xf0);

	
		// ADC Analog programmed for PTM_R4
		aic3268_write(codec, PAGE_1 + 0x3D, 0x00);
		
		// Power-up ADC Channel
		aic3268_write(codec, PAGE_0 + 0x51, 0xC0);
		aic3268_write(codec, PAGE_0 + 0x52, 0x00);