uint8_t AIC34_Master_Slave_Set(uint8_t i2c_addr,uint8_t select, unsigned int fs)
{

    if(select==MASTER)
    {
        uint8_t u_value=0;



        u_value=0;
        AIC34_ReadReg(i2c_addr,98,&u_value);
        u_value|=2<<4;             // GPIO1_x output = clock mux output divided by 1 (M = 1)
        u_value|=1<<3;             // GPIO1_x clock mux output = clock divider mux output
        AIC34_WriteReg(i2c_addr,98,u_value);

        u_value=0;
        AIC34_ReadReg(i2c_addr,102,&u_value);
        u_value|=1<<6;             // CLKDIV_IN uses GPIO2_x
        u_value|=1<<4;             // PLLCLK_IN uses GPIO2_x.
        u_value|=2<<0;             // N=2
        AIC34_WriteReg(i2c_addr,102,u_value);


        u_value=0;
        AIC34_ReadReg(i2c_addr,8,&u_value);
        u_value|=1<<7;             // BCLK_x (or GPIO2_x if programmed as BCLK_x) is an output (master mode).
        u_value|=1<<6;             // WCLK_x (or GPIO1_x if programmed as WCLK_x) is an output (master mode)
        u_value|=1<<5;             // 1: Place DOUT_x in high-impedance state when valid data is not being sent.
        u_value|=1<<4;             // BCLK_x (or GPIO2_x if programmed as BCLK_x) / WCLK_x (or GPIO1_x if programmed as
        // WCLK_x) continues to be transmitted when running in master mode, even if codec is powered down
        AIC34_WriteReg(i2c_addr,8,u_value);


        switch(fs)
        {
        case 48000:
            u_value=0;
            AIC34_ReadReg(i2c_addr,3,&u_value);
            u_value|=1<<0;                        //P=1
            AIC34_WriteReg(i2c_addr,3,u_value);
            u_value=0;
            AIC34_ReadReg(i2c_addr,3,&u_value);

            u_value=0;
            u_value|=0x08<<2;                      //J=8
            AIC34_WriteReg(i2c_addr,4,u_value);

            AIC34_WriteReg(i2c_addr,5,0);        //D=0
            AIC34_WriteReg(i2c_addr,6,0);

            u_value=0;
            AIC34_ReadReg(i2c_addr,11,&u_value);
            u_value|=1<<0;                        //P=1
            AIC34_WriteReg(i2c_addr,11,u_value);


            u_value=0;
            AIC34_ReadReg(i2c_addr,19,&u_value);
            u_value|=1<<2;
            AIC34_WriteReg(i2c_addr,19,u_value);

            u_value=0;
            AIC34_ReadReg(i2c_addr,22,&u_value);
            u_value|=1<<2;
            AIC34_WriteReg(i2c_addr,22,u_value);
            break;
        default:
            break;
        }
        AIC34_ReadReg(i2c_addr,3,&u_value);
        u_value|=1<<7;                        //PLL is enabled
        AIC34_WriteReg(i2c_addr,3,u_value);
    }
    return 1;
}