[C66xx_0] Version #: 0x01000105; string HYPLNK LLD Revision: 01.00.01.05:Nov 19 2012:16:04:15 [C66xx_0] About to do system setup (PLL, PSC, and DDR) [C66xx_0] Power domain is already enabled. You probably re-ran without device reset (which is OK) [C66xx_0] Constructed SERDES configs: PLL=0x00000228; RX=0x0046c485; TX=0x000cc305 [C66xx_0] system setup worked [C66xx_0] About to set up HyperLink Peripheral [C66xx_0] ============== begin registers before initialization =========== [C66xx_0] Revision register contents: [C66xx_0] Raw = 0x4e901900 [C66xx_0] Status register contents: [C66xx_0] Raw = 0x00002004 [C66xx_0] Link status register contents: [C66xx_0] Raw = 0x00000000 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00000001 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00000000 [C66xx_0] ============== end registers before initialization =========== [C66xx_0] Waiting for other side to come up ( 0) [C66xx_0] SERDES_STS (32 bits) contents: 0x03060c19; lock = 1 [C66xx_0] Waiting for other side to come up ( 1) [C66xx_0] Waiting for other side to come up ( 2) [C66xx_0] Waiting for other side to come up ( 3) [C66xx_0] Waiting for other side to come up ( 4) [C66xx_0] Waiting for other side to come up ( 5) [C66xx_0] Waiting for other side to come up ( 6) [C66xx_0] Waiting for other side to come up ( 7) [C66xx_0] Waiting for other side to come up ( 8) [C66xx_0] Waiting for other side to come up ( 9) [C66xx_0] Waiting for other side to come up ( 10) [C66xx_0] Waiting for other side to come up ( 11) [C66xx_0] Waiting for other side to come up ( 12) [C66xx_0] Waiting for other side to come up ( 13) [C66xx_0] Waiting for other side to come up ( 14) [C66xx_0] Waiting for other side to come up ( 15) [C66xx_0] Waiting for other side to come up ( 16) [C66xx_0] Waiting for other side to come up ( 17) [C66xx_0] Waiting for other side to come up ( 18) [C66xx_0] Waiting for other side to come up ( 19) [C66xx_0] Waiting for other side to come up ( 20) [C66xx_0] Waiting for other side to come up ( 21) [C66xx_0] Waiting for other side to come up ( 22) [C66xx_0] Waiting for other side to come up ( 23) [C66xx_0] Waiting for other side to come up ( 24) [C66xx_0] Waiting for other side to come up ( 25) [C66xx_0] Waiting for other side to come up ( 26) [C66xx_0] Waiting for other side to come up ( 27) [C66xx_0] Waiting for other side to come up ( 28) [C66xx_0] Waiting for other side to come up ( 29) [C66xx_0] Waiting for other side to come up ( 30) [C66xx_0] Waiting for other side to come up ( 31) [C66xx_0] Waiting for other side to come up ( 32) [C66xx_0] Waiting for other side to come up ( 33) [C66xx_0] Waiting for other side to come up ( 34) [C66xx_0] Waiting for other side to come up ( 35) [C66xx_0] Waiting for other side to come up ( 36) [C66xx_0] Waiting for other side to come up ( 37) [C66xx_0] Waiting for other side to come up ( 38) [C66xx_0] SERDES_STS (32 bits) contents: 0x00000001; lock = 1 [C66xx_0] ============== begin registers after initialization =========== [C66xx_0] Status register contents: [C66xx_0] Raw = 0x04400005 [C66xx_0] Link status register contents: [C66xx_0] Raw = 0xccf00cf0 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00006200 [C66xx_0] ============== end registers after initialization =========== [C66xx_0] Waiting 5 seconds to check link stability [C66xx_0] Precursors 0 Analysis: 0,1,0,1,1,0,0,1 [C66xx_0] Postcursors: 19 Analysis: 0,1,0,1,1,0,1,0 [C66xx_0] Link seems stable [C66xx_0] About to try to read remote registers [C66xx_0] ============== begin REMOTE registers after initialization =========== [C66xx_0] Status register contents: [C66xx_0] Raw = 0x0440000b [C66xx_0] Link status register contents: [C66xx_0] Raw = 0xfdf0bdf0 [C66xx_0] Control register contents: [C66xx_0] Raw = 0x00006200 [C66xx_0] ============== end REMOTE registers after initialization =========== [C66xx_0] Peripheral setup worked [C66xx_0] About to read/write once [C66xx_0] Single write test passed [C66xx_0] About to pass 65536 tokens; iteration = 0 [C66xx_0] === this is not an optimized example === [C66xx_0] Link Speed is 4 * 6.25 Gbps [C66xx_0] Passed 65536 tokens round trip (read+write through hyplnk) in 16247 Mcycles [C66xx_0] Approximately 247917 cycles per round-trip [C66xx_0] === this is not an optimized example === [C66xx_0] Checking statistics [C66xx_0] About to pass 65536 tokens; iteration = 1 [C66xx_0] fail 0 0 [C66xx_0] hyplnkExampleCPUTokenExchange failed: 1 [C66xx_0] Single write failed (when synchronizing bulk test)