void uppdrv_internal_reset()
{
        s32 ii;
        UN_UPICR_REG upicr_reg;

//reset begins
        UPPREGS.UPPCR.BIT.EN = 0; 
        while(UPPREGS.UPPCR.BIT.DB == 1);

        UPPREGS.UPPCR.BIT.SWRST = 1; 
        for(ii=0;ii<200;ii++);
        UPPREGS.UPPCR.BIT.SWRST = 0; 

        UPPREGS.UPPCR.BIT.FREE = 1;	//Free run is enabled.
        UPPREGS.UPPCR.BIT.SOFT = 0;	//Soft stop is disabled.
        UPPREGS.UPPCR.BIT.RTEMU = 0;	//Real-time emulation enabled. Peripheral halts transactions while program is halted.

        UPPREGS.UPDLB.BIT.AB = 1;	//Enable A-to-B digital loopback. Requires BA = 0 and the MODE bit in the uPP channel control register
(UPCTL) to be set to 3h.

//TODO: Duplex Mode 1. Channel A transmits and Channel B receives. Requires CHN = 1.


//TODO: MODE bit to be set to 3H


        UPPREGS.UPDLB.BIT.BA = 0;	//see above line
        UPPREGS.UPCTL.BIT.DDRDEMUX = 0;  //Disable the Double data rate demultiplexing mode. 

        UPPREGS.UPCTL.BIT.CHN = 1;	Dual channel mode


        uppdrv_duplex_mode(UPPM_DUPLEX1); 

/* For Channel A */
        UPPREGS.UPCTL.BIT.DRA = 0;	//Single data rate

        UPPREGS.UPCTL.BIT.IWA = 1;	//16-bit interface

        UPPREGS.UPCTL.BIT.DPWA = 0;	//No data packing (8-bit or 16-bit case)

        UPPREGS.UPCTL.BIT.DPFA = 0;	//Right-justified, zero extended


/* NOTE!! 32bit access */
        upicr_reg._DWORD = UPPREGS.UPICR._DWORD;
        upicr_reg.BIT.STARTPOLB = 1;	//TODO: need to chk 
        upicr_reg.BIT.ENAPOLA = 0;
        upicr_reg.BIT.WAITPOLA = 0;
        upicr_reg.BIT.STARTA = 0;
        upicr_reg.BIT.ENAA = 1;
        upicr_reg.BIT.WAITA = 0;
        upicr_reg.BIT.CLKDIVA = 2;
        upicr_reg.BIT.CLKINVA = 0;
        upicr_reg.BIT.TRISB = 0;	//TODO: need to chk 
        UPPREGS.UPICR._DWORD = upicr_reg._DWORD;
        UPPREGS.UPIVR.BIT.VALA = (u32)0x0004; 
        UPPREGS.UPTCR.BIT.TXSIZEA = 0; 

        UPPREGS.UPIES.BIT.DPEI = 0;
        UPPREGS.UPIES.BIT.UORI = 0;
/* B ch */
        UPPREGS.UPCTL.BIT.DRB = 0;	//Single data rate

        UPPREGS.UPCTL.BIT.IWB = 1;	//16-bit interface

        UPPREGS.UPCTL.BIT.DPWA = 0;	//TODO: again DPWA instead of DPWB
        UPPREGS.UPCTL.BIT.DPFB = 0;	//Right-justified, zero extended

//      UPPREGS.UPCTL.BIT.SDRXIL = 0;	//Disable. Each peripheral channel is associated with its own DMA channel


/* NOTE!! 32bit access */
        upicr_reg._DWORD = UPPREGS.UPICR._DWORD;
        upicr_reg.BIT.STARTPOLB = 0;
        upicr_reg.BIT.ENAPOLB = 0;
        upicr_reg.BIT.WAITPOLB = 0;
        upicr_reg.BIT.STARTB = 0;
        upicr_reg.BIT.ENAB = 1;
        upicr_reg.BIT.WAITB = 0;
        upicr_reg.BIT.CLKDIVB = 2;
        upicr_reg.BIT.CLKINVB = 0;
        upicr_reg.BIT.TRISB = 1;	//Channel B high-impedance state. Controls interface Channel B while idle in transmit mode. Only applies
when Channel B is configured in transmit mode using the MODE bit in the uPP channel control register
(UPCTL).

//TODO: Need to set MODE bit

        UPPREGS.UPICR._DWORD = upicr_reg._DWORD;

        UPPREGS.UPIVR.BIT.VALB = (u32)0x0003;
        UPPREGS.UPTCR.BIT.TXSIZEB = 0;	//64 bytes threshold value to tx
        UPPREGS.UPTCR.BIT.RDSIZEI = 0;	//64 bytes threshold value to rx (DMA ch 1)
        UPPREGS.UPTCR.BIT.RDSIZEQ = 0;	//64 bytes threshold value to rx (DMA ch 2)

        UPPREGS.UPIES._DWORD = 0x00000000;
        UPPREGS.UPIER._DWORD = 0x001f001f;	//TODO: Error occured?
        UPPREGS.UPIEC._DWORD = 0x001f001f;
        UPPREGS.UPPCR.BIT.EN = 1;
}