#------------------------------
# DAC/ADC CLOCK CONFIG
#------------------------------
# MCLK is 38.4MHz
# PLL_CLK = r*j.D/p = 1*5.1200/2 = 98.304 MHz 
# P=2, R=1 : XPPP RRRR
#android
#PLL_CLK = r*j.D/p = 1*5.1200/2 = 98.304 MHz 
# P=1, R=1 : XPPP RRRR
sreg[PLL_PR_POW] =  0b.0010001;
# J=5 :XXJJ JJJJ
# J=7 :XXJJ JJJJ
sreg[PLL_J] =  0b..000111;
# D= 1200. MSB=04 LSB=B0
# D= 1200. MSB=06 LSB=90
sreg[PLL_D_MSB] =  0x08;
sreg[PLL_D_LSB] =  0x48;
# DIV = 1 XVVV VVVV (128,1-127)
sreg[PLL_CKIN_DIV] =  0b.0000001;
# NDAC = 2: XVVV VVVV (128,1-127)
sreg[NDAC_DIV_POW] =  0b.0000101;
# MDAC = 8 : XVVV VVVV (128,1-127)
# MDAC = 7 : XVVV VVVV (128,1-127)
sreg[MDAC_DIV_POW] =  0b.0000011;
# DOSR = 128 DOSRMSB = 0x00 DOSRLSB = 0x80
sreg[DOSR_MSB] =  0x00;
sreg[DOSR_LSB] =  0x80;
# NADC NADC = 2
# NADC NADC = 7-->Android
sreg[NADC_DIV_POW] =  0b.0000101;
# MADC MADC = 48
# MADC MADC = 2 -->Android
sreg[MADC_DIV_POW] =  0b.000011;
# AOSR = 128
sreg[AOSR] =  128;

#------------------------------
# ASI1 CLOCKS
#------------------------------
# ASI1 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01
sreg[ASI1_BCLK_N_CNTL] =  0b......01;
# BCLK N DIVIDER = 4 : XVVV VVVV
sreg[ASI1_BCLK_N] =  0b.0000100;
# WCLK N DIVIDER = 32 : XVVV VVVV
sreg[ASI1_WCLK_N] =  0b.0100000;
# ASI1 BCLK WCLK OUTPUTS : XBBB XWWWW
# BCLK = BCLK DIV OUT
# WCLK = ASI1 WDIV
sreg[ASI1_BWCLK_OUT_CNTL] =  0b.000.010;

#------------------------------
# ASI2 CLOCKS
#------------------------------
# ASI2 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01
sreg[ASI2_BCLK_N_CNTL] =  0b......01;
# BCLK N DIVIDER = 4 : XVVV VVVV
sreg[ASI2_BCLK_N] =  0b.0000100;
# WCLK N DIVIDER = 32 : XVVV VVVV
sreg[ASI2_WCLK_N] =  0b.0100000;
# ASI2 BCLK WCLK OUTPUTS : XBBB XWWWW
# BCLK = ASI2 BDIV
# WCLK = DAC_FS
sreg[ASI2_BWCLK_OUT_CNTL] =  0b.010.000;

#------------------------------
# ASI3 CLOCKS
#------------------------------
# ASI3 BCLK DIVIDER CLOCK INPUT = DAC_MOD_CLOCK : XXXX XX01
sreg[ASI3_BCLK_N_CNTL] =  0b......01;
# BCLK N DIVIDER = 4 : XVVV VVVV
sreg[ASI3_BCLK_N] =  0b.0000100;
# WCLK N DIVIDER = 32 : XVVV VVVV
sreg[ASI3_WCLK_N] =  0b.0100000;
# ASI3 BCLK WCLK OUTPUTS : XBBB XWWWW
# BCLK = ASI3 BDIV
# WCLK = DAC_FS
sreg[ASI3_BWCLK_OUT_CNTL] =  0b.100.000;