#			--------------------------------------------------------------- page 0 is selected
w 30 00 00
#			# reg[  0][  1] = 0x01	; Initialize the device through software reset
> 01
#			--------------------------------------------------------------- page 1 is selected
w 30 00 01
#			# reg[  1][  1] = 0x08	; Disable weak AVDD to DVDD connection
> 08
#			# reg[  1][  2] = 0x00	; Enable Master Analog Power Control
> 00
#			# reg[  1][ 71] = 0x32	; Set the input power-up time to 3.1ms
w 30 47 32
#			# reg[  1][123] = 0x05	; Force REF charging time to 40ms
w 30 7b 05
#
# miniDSP code goes here
#
#			--------------------------------------------------------------- page 0 is selected
w 30 00 00
#			# reg[  0][ 60] = 0x00	; Use miniDSP_D for signal processing
# w 30 3c 00
#			# reg[  0][ 61] = 0x00	; Use miniDSP_A for signal processing
# > 00
#			# reg[  0][ 17] = 0x08	; 8x Interpolation
w 30 11 08
#			# reg[  0][ 23] = 0x04	; 4x Decimation
w 30 17 04
#			
w 30 0f 03
#			
> 88
#			
w 30 15 03
#			
> 88
#			--------------------------------------------------------------- page 8 is selected
# w 30 00 08
#			# reg[  8][  1] = 0x04	; adaptive mode for ADC
# > 04
#			--------------------------------------------------------------- page 44 is selected
# w 30 00 2c
#			# reg[ 44][  1] = 0x04	; adaptive mode for DAC
# > 04


#     --------------------------------------------------------------- page 1 is selected
w 30 00 01
#     # reg[1][1 ] = 0x08     ; reg(1)(0x01 => 1 )     Crude avdd disabled
> 08
#     # reg[1][2 ] = 0x01     ; reg(1)(0x02 => 2 )     AVDD LDO power up
> 01
#     # reg[1][10] = 0x03     ;  LDOIN 1,8-3,6V
w 30 0A 03
#     --------------------------------------------------------------- page 0 is selected
w 30 00 00
#     # reg[0][04] = 0x03     ; PLL_clkin = MCLK,codec_clkin = PLL_CLK
w 30 04 03
#     # reg[0][05] = 0xD1     ; PLL Power up, P = 5, R = 1
> D1
#     # reg[0][06] = 0x13     ; J = 19; 80 MHz <= PLL_CLK <= 110 MHz; PLL_CLK = (19.6608/5 * 25MHz) = 98.304MHz
> 13
#     # reg[0][07] = 0x19     ; D = 6608, D(13:8) = 0x19
> 19
#     # reg[0][08] = 0xD0     ; D(7:0) = 0xD0
> D0
#     # reg[0][11] = 0x82     ; NDAC is powered up and set to 2
w 30 0b 82
#     # reg[0][12] = 0x88     ; MDAC is powered up and set to 8
> 88
#     # reg[0][13] = 0x03     ; DOSR = 768, DOSR(9:8) = 0
> 03
#     # reg[0][14] = 0x00     ; DOSR(7:0) = 768
> 00
#     # reg[0][29] = 0x01     ; bdiv_clkin = dac_mod_clk
w 30 1d 01
#     # reg[0][30] = 0x8c     ; blk_N = 12
w 30 1e 8c
#     # reg[0][18] = 0x88      --powerup NADC and value is 8
w 30 12 88
#     # reg[0][19] = 0x8C      --Powerup MADC and value is 12
> 8C
#     # reg[0][20] = 0x40      --AOSR is 128
> 80
#     # reg[0][27] = 0x4c     ; mode is dsp,wordlength is 16, codec is bclk and wclk master
w 30 1b 4c
#     # reg[0][63] = 0xd6     ;11010110b     ; POWERUP DAC left and right channels (soft step disable)
w 30 3f d6
#     # reg[0][81] = 0xc2     ;11000010b     ; -- POWERUP ADC left and left channel (soft step disable)
w 30 51 c2
#     # reg[0][82] = 0x00     ;00000000b     ; -- unmute ADC
> 00



#############################################################
#                       Select Page 1
w 30 00 01
#                      Turn On Mic Bias generated from LDOIN
w 30 33 68
### d 30


###############  IN 3 SET UP START *************************
#
#                      IN2_L is selected for left P 10k
w 30 34 10
#
#                      IN2_R is selected for left M 10k
w 30 36 10
#
#                      IN1_R is selected for right P 10k
w 30 37 40
#
#                      IN1_L is selected for right M 10k
w 30 39 10
#
###############  IN 3 SET UP END ****************************

#                      unmute left mic PGA
w 30 3b 48
#                      unmute right mic PGA
w 30 3c 00
#**********  ENABLE DAC and HP OUTPUTS *********************
w 30 00 01

#########################################################

#                      Power up LOL and LOR driver
w 30 09 0c
#                      LDAC AFIR routed to LOL
w 30 0e 08
#                      RDAC AFIR routed to LOR
w 30 0f 08
#                      LOL unmuted with 0dB gain
w 30 12 00
#                      LOR unmuted with 0dB gain
w 30 13 00
#                      Page 0 selected
w 30 00 00
#                      L&R DAC powerup Ldata-LDAC Rdata-RDAC
w 30 3f d6
#                      DAC left digital PGA
w 30 41 00

#                      Left and Right DAC unmuted with indep.  vol. ctrl
w 30 40 00