diff --git a/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis.c b/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis.c
index 2e18e12..731e4a1 100755
--- a/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis.c
+++ b/demos/mcfw_api_demos/mcfw_demo/demo_vdec_vdis.c
@@ -180,7 +180,7 @@ Void VdecVdis_start()
                            vdisParams.deviceParams[VDIS_DEV_HDMI].resolution;
     vdisParams.deviceParams[VDIS_DEV_SD].resolution     = VSYS_STD_NTSC;
 
-    Vdis_tiedVencInit(VDIS_DEV_HDCOMP, VDIS_DEV_DVO2, &vdisParams);
+    Vdis_tiedVencInit(VDIS_DEV_HDCOMP, VDIS_DEV_HDMI, &vdisParams);
 
 
 
diff --git a/mcfw/src_bios6/links_m3vpss/system/system_dctrl.c b/mcfw/src_bios6/links_m3vpss/system/system_dctrl.c
index 819118d..80db3de 100755
--- a/mcfw/src_bios6/links_m3vpss/system/system_dctrl.c
+++ b/mcfw/src_bios6/links_m3vpss/system/system_dctrl.c
@@ -27,13 +27,13 @@ Vps_DcConfig gSystem_dctrlTriDisplayConfigDvo2 = {
      {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND}     ,
      {VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
      {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}     ,
-     {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
+     {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDMI_BLEND}     ,
      {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND}     ,
      {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}     ,
      {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}     ,
      {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}     ,
      {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND}     ,
-     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND},
+     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDMI_BLEND},
      {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_HDMI_BLEND},
      {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
      {VPS_DC_AUX_INPUT_PATH, VPS_DC_HDCOMP_MUX}
@@ -69,7 +69,7 @@ Vps_DcConfig gSystem_dctrlTriDisplayConfigDvo2 = {
        }
       }
      ,
-     (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
+     (VPS_DC_VENC_HDMI | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                             * mask */
      4u                                                    /* Number of VENCs
                                                             */
@@ -87,12 +87,12 @@ Vps_DcConfig gSystem_dctrlTriDisplayConfigHdmi = {
      {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND},
      {VPS_DC_BP1_INPUT_PATH, VPS_DC_VCOMP_MUX},
      {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP},
-     {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_DVO2_BLEND},
+     {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND},
      {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX},
      {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND},
      {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND},
      {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDCOMP_BLEND},
-     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND},
+     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDMI_BLEND},
      {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_SDVENC_BLEND},
      {VPS_DC_GRPX2_INPUT_PATH, VPS_DC_HDMI_BLEND},
      {VPS_DC_MAIN_INPUT_PATH, VPS_DC_VCOMP},
@@ -619,7 +619,17 @@ Int32 System_displayCtrlInit(VDIS_PARAMS_S * pPrm)
 
     UTILS_assert(retVal == FVID2_SOK);
 
-
+    {
+        Vps_DcRgbColor transparencyPixel;
+        Int32 System_displayCtrlSetVideoLayerPriority(UInt32 compNodeId,
+                                                      UInt32 cigNodeId,
+                                                      Vps_DcRgbColor transparencyPixel,
+                                                      UInt8 alphaValue);
+
+        transparencyPixel.r = transparencyPixel.g = transparencyPixel.b = 0;
+        System_displayCtrlSetVideoLayerPriority(VPS_DC_HDMI_BLEND,VPS_DC_CIG_PIP_OUTPUT,transparencyPixel,0x80);
+        System_displayCtrlSetVideoLayerPriority(VPS_DC_HDMI_BLEND,VPS_DC_CIG_NON_CONSTRAINED_OUTPUT,transparencyPixel,0x80);
+    }
     return retVal;
 }
 
@@ -709,7 +719,8 @@ Int32 System_displayCtrlSetCprocSetting(VDIS_CPROC_S *pPrm)
+Int32 System_displayCtrlSetVideoLayerPriority(UInt32 compNodeId,
+                                              UInt32 cigNodeId,
+                                              Vps_DcRgbColor transparencyPixel,
+                                              UInt8 alphaValue)
+{
+    Int32           retVal = FVID2_SOK;
+    Vps_DcCompRtConfig compRtConfig;
+    Vps_DcCigRtConfig  cigRtConfig;
+
+    compRtConfig.nodeId = compNodeId; //VPS_DC_HDMI_BLEND;
+    retVal = FVID2_control(gSystem_objVpss.fvidDisplayCtrl,
+                           IOCTL_VPS_DCTRL_GET_COMP_RTCONFIG,
+                           &compRtConfig,NULL);
+    UTILS_assert(retVal == FVID2_SOK);
+
+    compRtConfig.nodeId = compNodeId;//VPS_DC_HDMI_BLEND;
+    compRtConfig.isGlobalReorderEnable = TRUE;
+    compRtConfig.displayOrder[VPS_DC_COMP_DISPLAY_VID_ORDER] = 0x3;
+    compRtConfig.displayOrder[VPS_DC_COMP_DISPLAY_G0_ORDER] = 0x0;
+    compRtConfig.displayOrder[VPS_DC_COMP_DISPLAY_G1_ORDER] = 0x1;
+    compRtConfig.displayOrder[VPS_DC_COMP_DISPLAY_G2_ORDER] = 0x2;
+    retVal = FVID2_control(gSystem_objVpss.fvidDisplayCtrl,
+                           IOCTL_VPS_DCTRL_SET_COMP_RTCONFIG,
+                           &compRtConfig,NULL);
+    UTILS_assert(retVal == FVID2_SOK);
+    Vps_printf("DCRTL:Reorder of video and grpx");
+
+    cigRtConfig.nodeId = cigNodeId;//VPS_DC_CIG_NON_CONSTRAINED_OUTPUT;
+    retVal = FVID2_control(gSystem_objVpss.fvidDisplayCtrl,
+                           IOCTL_VPS_DCTRL_GET_CIG_RTCONFIG,
+                           &cigRtConfig,NULL);
+    UTILS_assert(retVal == FVID2_SOK);
+
+    cigRtConfig.nodeId = cigNodeId;//VPS_DC_CIG_NON_CONSTRAINED_OUTPUT;
+    cigRtConfig.transparency = TRUE;
+    cigRtConfig.mask = VPS_DC_CIG_TM_MASK_3_LSB;
+    cigRtConfig.transColor.r = transparencyPixel.r;// 0x0;
+    cigRtConfig.transColor.g = transparencyPixel.g;// 0x0;
+    cigRtConfig.transColor.b = transparencyPixel.b;// 0x0;
+    cigRtConfig.alphaBlending = TRUE;
+    cigRtConfig.alphaValue    = alphaValue;
+    retVal = FVID2_control(gSystem_objVpss.fvidDisplayCtrl,
+                           IOCTL_VPS_DCTRL_SET_CIG_RTCONFIG,
+                           &cigRtConfig,NULL);
+    UTILS_assert(retVal == FVID2_SOK);
+    Vps_printf("DCRTL:Setting of transparency pixel");
+    return retVal;
+}
+