#ifndef _PINMUX_H_
#define _PINMUX_H_

/*
 * DISABLED - Disabled
 * FCN1 - Mux Fcn 1
 * FCN2 - Mux Fcn 2
 * FCN3 - Mux Fcn 3
 * FCN4 - Mux Fcn 4
 * FCN5 - Mux Fcn 5
 * FCN6 - Mux Fcn 6
 * FCN7 - Mux Fcn 7
 * FCN8 - Mux Fcn 8
 * IDIS - Receiver disabled
 * IEN - Receiver enabled
 * IPD - Internal pull-down
 * IPU - Internal pull-up
 * DIS - Internal pull disabled
 */

#define MUX_EVM() \

/* Design Status: NO ERRORS */

MUX_VAL(PINCNTL1, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL2, (IEN | IPU | FCN8 )) /* GP0[0] */\
MUX_VAL(PINCNTL3, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL4, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL5, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL6, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL7, (IEN | IPU | FCN2 )) /* SPI[1]_SCS[1] */\
MUX_VAL(PINCNTL8, (IEN | IPU | FCN8 )) /* GP0[1] */\
MUX_VAL(PINCNTL9, (IEN | IPU | FCN8 )) /* GP0[2] */\
MUX_VAL(PINCNTL10, (IEN | IPU | FCN8 )) /* GP0[3] */\
MUX_VAL(PINCNTL11, (IEN | IPU | FCN8 )) /* GP0[4] */\
MUX_VAL(PINCNTL12, (IEN | IPU | FCN8 )) /* GP0[5] */\
MUX_VAL(PINCNTL13, (IEN | IPU | FCN8 )) /* GP0[6] */\
MUX_VAL(PINCNTL14, (IEN | IPD | FCN4 )) /* MCA[3]_AHCLKX */\
MUX_VAL(PINCNTL15, (IEN | IPD | FCN8 )) /* GP0[8] */\
MUX_VAL(PINCNTL16, (IEN | IPD | FCN3 )) /* MCA[2]_AHCLKX */\
MUX_VAL(PINCNTL17, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL18, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL19, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL20, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL21, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL22, (IEN | IPU | FCN6 )) /* I2C[3]_SCL_MUX0 */\
MUX_VAL(PINCNTL23, (IEN | IPU | FCN6 )) /* I2C[3]_SDA_MUX0 */\
MUX_VAL(PINCNTL24, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL25, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL26, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL27, (IEN | IPD | FCN2 )) /* MCB_DR */\
MUX_VAL(PINCNTL28, (IEN | IPD | FCN2 )) /* MCB_DX */\
MUX_VAL(PINCNTL29, (IEN | IPD | FCN2 )) /* MCB_FSX */\
MUX_VAL(PINCNTL30, (IEN | IPD | FCN2 )) /* MCB_CLKX */\
MUX_VAL(PINCNTL31, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL32, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL33, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL34, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL35, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL36, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL37, (IEN | IPD | FCN2 )) /* MCB_FSR_MUX0 */\
MUX_VAL(PINCNTL38, (IEN | IPD | FCN2 )) /* MCB_CLKR_MUX0 */\
MUX_VAL(PINCNTL39, (IEN | IPU | FCN1 )) /* MCA[2]_ACLKX */\
MUX_VAL(PINCNTL40, (IEN | IPU | FCN1 )) /* MCA[2]_AFSX */\
MUX_VAL(PINCNTL41, (IEN | IPU | FCN1 )) /* MCA[2]_AXR[0] */\
MUX_VAL(PINCNTL42, (IEN | IPU | FCN1 )) /* MCA[2]_AXR[1] */\
MUX_VAL(PINCNTL43, (IEN | IPD | FCN1 )) /* MCA[2]_AXR[2] */\
MUX_VAL(PINCNTL44, (IEN | IPD | FCN1 )) /* MCA[2]_AXR[3] */\
MUX_VAL(PINCNTL45, (IEN | IPD | FCN1 )) /* MCA[3]_ACLKX */\
MUX_VAL(PINCNTL46, (IEN | IPD | FCN1 )) /* MCA[3]_AFSX */\
MUX_VAL(PINCNTL47, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[0] */\
MUX_VAL(PINCNTL48, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[1] */\
MUX_VAL(PINCNTL49, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[2] */\
MUX_VAL(PINCNTL50, (IEN | IPD | FCN1 )) /* MCA[3]_AXR[3] */\
MUX_VAL(PINCNTL51, (IEN | IPD | FCN8 )) /* GP0[21]_MUX1 */\
MUX_VAL(PINCNTL52, (IEN | IPD | FCN8 )) /* GP0[22]_MUX1 */\
MUX_VAL(PINCNTL53, (IEN | IPD | FCN8 )) /* GP0[23]_MUX1 */\
MUX_VAL(PINCNTL54, (IEN | IPD | FCN8 )) /* GP0[24]_MUX1 */\
MUX_VAL(PINCNTL55, (IEN | IPD | FCN8 )) /* GP0[25]_MUX1 */\
MUX_VAL(PINCNTL56, (IEN | IPD | FCN8 )) /* GP0[26]_MUX1 */\
MUX_VAL(PINCNTL57, (IEN | IPD | FCN8 )) /* GP0[27]_MUX1 */\
MUX_VAL(PINCNTL58, (IEN | IPD | FCN8 )) /* GP0[28]_MUX1 */\
MUX_VAL(PINCNTL59, (IEN | IPD | FCN4 )) /* UART2_RXD_MUX1 */\
MUX_VAL(PINCNTL60, (IEN | IPD | FCN8 )) /* GP0[30] */\
MUX_VAL(PINCNTL61, (IEN | IPD | FCN4 )) /* UART2_TXD_MUX1 */\
MUX_VAL(PINCNTL62, (IEN | IPD | FCN8 )) /* GP1[7]_MUX1 */\
MUX_VAL(PINCNTL63, (IEN | IPU | FCN8 )) /* GP1[8]_MUX1 */\
MUX_VAL(PINCNTL64, (IEN | IPD | FCN8 )) /* GP1[9]_MUX1 */\
MUX_VAL(PINCNTL65, (IEN | IPU | FCN8 )) /* GP1[10]_MUX1 */\
MUX_VAL(PINCNTL68, (IEN | IPU | FCN8 )) /* GP1[0] */\
MUX_VAL(PINCNTL69, (IEN | IPU | FCN8 )) /* GP1[1] */\
MUX_VAL(PINCNTL70, (IEN | IPU | FCN1 )) /* UART0_RXD */\
MUX_VAL(PINCNTL71, (IEN | IPU | FCN1 )) /* UART0_TXD */\
MUX_VAL(PINCNTL72, (IEN | IPU | FCN2 )) /* UART4_RXD_MUX3 */\
MUX_VAL(PINCNTL73, (IEN | IPU | FCN2 )) /* UART4_TXD_MUX3 */\
MUX_VAL(PINCNTL74, (IEN | IPU | FCN2 )) /* UART3_RXD_MUX0 */\
MUX_VAL(PINCNTL75, (IEN | IPU | FCN2 )) /* UART3_TXD_MUX0 */\
MUX_VAL(PINCNTL76, (IEN | IPU | FCN3 )) /* UART1_TXD_MUX0 */\
MUX_VAL(PINCNTL77, (IEN | IPU | FCN3 )) /* UART1_RXD_MUX0 */\
MUX_VAL(PINCNTL78, (IEN | IPU | FCN1 )) /* I2C[1]_SCL */\
MUX_VAL(PINCNTL79, (IEN | IPU | FCN1 )) /* I2C[1]_SDA */\
MUX_VAL(PINCNTL80, (IEN | IPU | FCN8 )) /* GP1[6] */\
MUX_VAL(PINCNTL81, (IEN | IPU | FCN1 )) /* SPI[0]_SCS[0] */\
MUX_VAL(PINCNTL82, (IEN | IPU | FCN1 )) /* SPI[0]_SCLK */\
MUX_VAL(PINCNTL83, (IEN | IPU | FCN1 )) /* SPI[0]_D[1] */\
MUX_VAL(PINCNTL84, (IEN | IPU | FCN1 )) /* SPI[0]_D[0] */\
MUX_VAL(PINCNTL85, (IEN | IPU | FCN8 )) /* GP1[16]_MUX1 */\
MUX_VAL(PINCNTL86, (IEN | IPU | FCN1 )) /* SPI[1]_SCLK */\
MUX_VAL(PINCNTL87, (IEN | IPU | FCN1 )) /* SPI[1]_D[1] */\
MUX_VAL(PINCNTL88, (IEN | IPU | FCN1 )) /* SPI[1]_D[0] */\
MUX_VAL(PINCNTL89, (IEN | DIS | FCN1 )) /* GPMC_D[0] */\
MUX_VAL(PINCNTL90, (IEN | DIS | FCN1 )) /* GPMC_D[1] */\
MUX_VAL(PINCNTL91, (IEN | DIS | FCN1 )) /* GPMC_D[2] */\
MUX_VAL(PINCNTL92, (IEN | DIS | FCN1 )) /* GPMC_D[3] */\
MUX_VAL(PINCNTL93, (IEN | DIS | FCN1 )) /* GPMC_D[4] */\
MUX_VAL(PINCNTL94, (IEN | DIS | FCN1 )) /* GPMC_D[5] */\
MUX_VAL(PINCNTL95, (IEN | DIS | FCN1 )) /* GPMC_D[6] */\
MUX_VAL(PINCNTL96, (IEN | DIS | FCN1 )) /* GPMC_D[7] */\
MUX_VAL(PINCNTL97, (IEN | DIS | FCN1 )) /* GPMC_D[8] */\
MUX_VAL(PINCNTL98, (IEN | DIS | FCN1 )) /* GPMC_D[9] */\
MUX_VAL(PINCNTL99, (IEN | DIS | FCN1 )) /* GPMC_D[10] */\
MUX_VAL(PINCNTL100, (IEN | DIS | FCN1 )) /* GPMC_D[11] */\
MUX_VAL(PINCNTL101, (IEN | DIS | FCN1 )) /* GPMC_D[12] */\
MUX_VAL(PINCNTL102, (IEN | DIS | FCN1 )) /* GPMC_D[13] */\
MUX_VAL(PINCNTL103, (IEN | DIS | FCN1 )) /* GPMC_D[14] */\
MUX_VAL(PINCNTL104, (IEN | DIS | FCN1 )) /* GPMC_D[15] */\
MUX_VAL(PINCNTL105, (IEN | IPD | FCN1 )) /* GPMC_A[16] */\
MUX_VAL(PINCNTL106, (IEN | IPD | FCN1 )) /* GPMC_A[17] */\
MUX_VAL(PINCNTL107, (IEN | IPD | FCN1 )) /* GPMC_A[18] */\
MUX_VAL(PINCNTL108, (IEN | IPD | FCN1 )) /* GPMC_A[19] */\
MUX_VAL(PINCNTL109, (IEN | IPU | FCN3 )) /* SPI[2]_SCS[1] */\
MUX_VAL(PINCNTL110, (IEN | IPD | FCN3 )) /* SPI[2]_D[0]_MUX0 */\
MUX_VAL(PINCNTL111, (IEN | IPU | FCN3 )) /* SPI[2]_D[1]_MUX0 */\
MUX_VAL(PINCNTL112, (IEN | IPD | FCN3 )) /* SPI[2]_SCLK_MUX0 */\
MUX_VAL(PINCNTL113, (IEN | IPU | FCN8 )) /* GP1[19] */\
MUX_VAL(PINCNTL114, (IEN | IPU | FCN8 )) /* GP1[20] */\
MUX_VAL(PINCNTL115, (IEN | IPU | FCN8 )) /* GP1[21] */\
MUX_VAL(PINCNTL116, (IEN | IPU | FCN8 )) /* GP1[22] */\
MUX_VAL(PINCNTL117, (IEN | IPU | FCN2 )) /* GPMC_A[1]_MUX1 */\
MUX_VAL(PINCNTL118, (IEN | IPU | FCN2 )) /* GPMC_A[2]_MUX1 */\
MUX_VAL(PINCNTL119, (IEN | IPU | FCN2 )) /* GPMC_A[3]_MUX1 */\
MUX_VAL(PINCNTL120, (IEN | IPU | FCN2 )) /* GPMC_A[4]_MUX1 */\
MUX_VAL(PINCNTL121, (IEN | IPU | FCN8 )) /* GP1[15]_MUX1 */\
MUX_VAL(PINCNTL122, (IEN | IPU | FCN1 )) /* GPMC_CS[0] */\
MUX_VAL(PINCNTL123, (IEN | IPU | FCN1 )) /* GPMC_CS[1] */\
MUX_VAL(PINCNTL124, (IEN | IPU | FCN1 )) /* GPMC_CS[2] */\
MUX_VAL(PINCNTL125, (IEN | IPU | FCN3 )) /* SPI[2]_SCS[0] */\
MUX_VAL(PINCNTL126, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL127, (IEN | IPU | FCN1 )) /* GPMC_CLK */\
MUX_VAL(PINCNTL128, (IEN | IPU | FCN1 )) /* GPMC_ADV_ALE */\
MUX_VAL(PINCNTL129, (IEN | IPU | FCN1 )) /* GPMC_OE_RE */\
MUX_VAL(PINCNTL130, (IEN | IPU | FCN1 )) /* GPMC_WE */\
MUX_VAL(PINCNTL131, (IEN | IPD | FCN1 )) /* GPMC_BE[0]_CLE */\
MUX_VAL(PINCNTL132, (IEN | IPD | FCN1 )) /* GPMC_BE[1] */\
MUX_VAL(PINCNTL133, (IEN | IPU | FCN1 )) /* GPMC_WAIT[0] */\
MUX_VAL(PINCNTL134, (IEN | IPD | FCN6 )) /* CLKOUT0 */\
MUX_VAL(PINCNTL135, (IEN | IPU | FCN8 )) /* GP2[0] */\
MUX_VAL(PINCNTL136, (IEN | IPU | FCN8 )) /* GP2[1] */\
MUX_VAL(PINCNTL137, (IEN | IPD | FCN8 )) /* GP2[2]_MUX1 */\
MUX_VAL(PINCNTL138, (IEN | IPU | FCN8 )) /* GP2[3] */\
MUX_VAL(PINCNTL139, (IEN | IPU | FCN8 )) /* GP2[4] */\
MUX_VAL(PINCNTL140, (IEN | IPD | FCN8 )) /* GP1[11]_MUX1 */\
MUX_VAL(PINCNTL141, (IEN | IPD | FCN8 )) /* GP1[12]_MUX1 */\
MUX_VAL(PINCNTL142, (IEN | IPD | FCN8 )) /* GP2[7] */\
MUX_VAL(PINCNTL143, (IEN | IPD | FCN8 )) /* GP2[8] */\
MUX_VAL(PINCNTL144, (IEN | IPD | FCN8 )) /* GP2[9] */\
MUX_VAL(PINCNTL145, (IEN | IPD | FCN8 )) /* GP2[10] */\
MUX_VAL(PINCNTL146, (IEN | IPD | FCN8 )) /* GP2[11] */\
MUX_VAL(PINCNTL147, (IEN | IPD | FCN8 )) /* GP2[12] */\
MUX_VAL(PINCNTL148, (IEN | IPD | FCN8 )) /* GP2[13] */\
MUX_VAL(PINCNTL149, (IEN | IPD | FCN8 )) /* GP2[14] */\
MUX_VAL(PINCNTL150, (IEN | IPD | FCN8 )) /* GP2[15] */\
MUX_VAL(PINCNTL151, (IEN | IPD | FCN8 )) /* GP2[16] */\
MUX_VAL(PINCNTL152, (IEN | IPD | FCN8 )) /* GP2[17] */\
MUX_VAL(PINCNTL153, (IEN | IPD | FCN8 )) /* GP2[18] */\
MUX_VAL(PINCNTL154, (IEN | IPD | FCN8 )) /* GP2[19] */\
MUX_VAL(PINCNTL155, (IEN | IPD | FCN8 )) /* GP2[20] */\
MUX_VAL(PINCNTL156, (IEN | IPU | FCN8 )) /* GP0[10]_MUX0 */\
MUX_VAL(PINCNTL157, (IEN | IPD | FCN4 )) /* EMAC[1]_RMRXER_MUX1 */\
MUX_VAL(PINCNTL158, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[1]_MUX1 */\
MUX_VAL(PINCNTL159, (IEN | IPU | FCN4 )) /* EMAC[1]_RMRXD[0]_MUX1 */\
MUX_VAL(PINCNTL160, (IEN | IPD | FCN4 )) /* EMAC[1]_RMCRSDV_MUX1 */\
MUX_VAL(PINCNTL161, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[0]_MUX1 */\
MUX_VAL(PINCNTL162, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXD[1]_MUX1 */\
MUX_VAL(PINCNTL163, (IEN | IPD | FCN4 )) /* EMAC[1]_RMTXEN_MUX1 */\
MUX_VAL(PINCNTL164, (IEN | IPU | FCN8 )) /* GP0[18]_MUX0 */\
MUX_VAL(PINCNTL165, (IEN | IPU | FCN8 )) /* GP0[19]_MUX0 */\
MUX_VAL(PINCNTL166, (IEN | IPU | FCN8 )) /* GP0[20]_MUX0 */\
MUX_VAL(PINCNTL167, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL168, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL169, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL170, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL171, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL172, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL173, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL174, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL175, (IEN | IPD | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL176, (IEN | IPD | FCN1 )) /* VOUT[0]_CLK */\
MUX_VAL(PINCNTL177, (IEN | IPD | FCN1 )) /* VOUT[0]_HSYNC */\
MUX_VAL(PINCNTL178, (IEN | IPD | FCN1 )) /* VOUT[0]_VSYNC */\
MUX_VAL(PINCNTL179, (IEN | IPD | FCN8 )) /* GP2[21] */\
MUX_VAL(PINCNTL180, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[2] */\
MUX_VAL(PINCNTL181, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[3] */\
MUX_VAL(PINCNTL182, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[4] */\
MUX_VAL(PINCNTL183, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[5] */\
MUX_VAL(PINCNTL184, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[6] */\
MUX_VAL(PINCNTL185, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[7] */\
MUX_VAL(PINCNTL186, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[8] */\
MUX_VAL(PINCNTL187, (IEN | IPD | FCN1 )) /* VOUT[0]_B_CB_C[9] */\
MUX_VAL(PINCNTL188, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[2] */\
MUX_VAL(PINCNTL189, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[3] */\
MUX_VAL(PINCNTL190, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[4] */\
MUX_VAL(PINCNTL191, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[5] */\
MUX_VAL(PINCNTL192, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[6] */\
MUX_VAL(PINCNTL193, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[7] */\
MUX_VAL(PINCNTL194, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[8] */\
MUX_VAL(PINCNTL195, (IEN | IPD | FCN1 )) /* VOUT[0]_G_Y_YC[9] */\
MUX_VAL(PINCNTL196, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[2] */\
MUX_VAL(PINCNTL197, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[3] */\
MUX_VAL(PINCNTL198, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[4] */\
MUX_VAL(PINCNTL199, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[5] */\
MUX_VAL(PINCNTL200, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[6] */\
MUX_VAL(PINCNTL201, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[7] */\
MUX_VAL(PINCNTL202, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[8] */\
MUX_VAL(PINCNTL203, (IEN | IPD | FCN1 )) /* VOUT[0]_R_CR[9] */\
MUX_VAL(PINCNTL204, (IEN | IPD | FCN3 )) /* VIN[1]A_HSYNC */\
MUX_VAL(PINCNTL205, (IEN | IPD | FCN3 )) /* VIN[1]A_VSYNC */\
MUX_VAL(PINCNTL206, (IEN | IPD | FCN3 )) /* VIN[1]A_FLD */\
MUX_VAL(PINCNTL207, (IEN | IPD | FCN3 )) /* VIN[1]A_CLK */\
MUX_VAL(PINCNTL208, (IEN | IPD | FCN3 )) /* VIN[1]A_D[0] */\
MUX_VAL(PINCNTL209, (IEN | IPD | FCN3 )) /* VIN[1]A_D[1] */\
MUX_VAL(PINCNTL210, (IEN | IPD | FCN3 )) /* VIN[1]A_D[2] */\
MUX_VAL(PINCNTL211, (IEN | IPD | FCN3 )) /* VIN[1]A_D[3] */\
MUX_VAL(PINCNTL212, (IEN | IPD | FCN3 )) /* VIN[1]A_D[4] */\
MUX_VAL(PINCNTL213, (IEN | IPD | FCN3 )) /* VIN[1]A_D[5] */\
MUX_VAL(PINCNTL214, (IEN | IPD | FCN3 )) /* VIN[1]A_D[6] */\
MUX_VAL(PINCNTL215, (IEN | IPD | FCN3 )) /* VIN[1]A_D[8] */\
MUX_VAL(PINCNTL216, (IEN | IPD | FCN3 )) /* VIN[1]A_D[9] */\
MUX_VAL(PINCNTL217, (IEN | IPD | FCN3 )) /* VIN[1]A_D[10] */\
MUX_VAL(PINCNTL218, (IEN | IPD | FCN3 )) /* VIN[1]A_D[11] */\
MUX_VAL(PINCNTL219, (IEN | IPD | FCN3 )) /* VIN[1]A_D[12] */\
MUX_VAL(PINCNTL220, (IEN | IPD | FCN3 )) /* VIN[1]A_D[13] */\
MUX_VAL(PINCNTL221, (IEN | IPD | FCN3 )) /* VIN[1]A_D[14] */\
MUX_VAL(PINCNTL222, (IEN | IPD | FCN3 )) /* VIN[1]A_D[15] */\
MUX_VAL(PINCNTL223, (IEN | IPD | FCN3 )) /* VIN[1]A_D[16] */\
MUX_VAL(PINCNTL224, (IEN | IPD | FCN3 )) /* VIN[1]A_D[17] */\
MUX_VAL(PINCNTL225, (IEN | IPD | FCN3 )) /* VIN[1]A_D[18] */\
MUX_VAL(PINCNTL226, (IEN | IPD | FCN3 )) /* VIN[1]A_D[19] */\
MUX_VAL(PINCNTL227, (IEN | IPD | FCN3 )) /* VIN[1]A_D[20] */\
MUX_VAL(PINCNTL228, (IEN | IPU | FCN3 )) /* VIN[1]A_D[21] */\
MUX_VAL(PINCNTL229, (IEN | IPU | FCN3 )) /* VIN[1]A_D[22] */\
MUX_VAL(PINCNTL230, (IEN | IPD | FCN3 )) /* VIN[1]A_D[23] */\
MUX_VAL(PINCNTL231, (IEN | IPU | FCN3 )) /* VIN[1]A_D[7] */\
MUX_VAL(PINCNTL232, (IEN | IPD | FCN1 )) /* EMAC_RMREFCLK */\
MUX_VAL(PINCNTL233, (IEN | IPU | FCN1 )) /* MDCLK */\
MUX_VAL(PINCNTL234, (IEN | IPU | FCN1 )) /* MDIO */\
MUX_VAL(PINCNTL235, (IEN | IPD | FCN1 )) /* EMAC[0]_MTCLK/EMAC[0]_RGRXC */\
MUX_VAL(PINCNTL236, (IEN | IPD | FCN1 )) /* EMAC[0]_MCOL/EMAC[0]_RGRXCTL */\
MUX_VAL(PINCNTL237, (IEN | IPD | FCN1 )) /* EMAC[0]_MCRS/EMAC[0]_RGRXD[2] */\
MUX_VAL(PINCNTL238, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXER/EMAC[0]_RGTXCTL */\
MUX_VAL(PINCNTL239, (IEN | IPD | FCN1 )) /* EMAC[0]_MRCLK/EMAC[0]_RGTXC */\
MUX_VAL(PINCNTL240, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[0]/EMAC[0]_RGTXD[0] */\
MUX_VAL(PINCNTL241, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[1]/EMAC[0]_RGRXD[0] */\
MUX_VAL(PINCNTL242, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[2]/EMAC[0]_RGRXD[1] */\
MUX_VAL(PINCNTL243, (IEN | IPD | FCN5 )) /* GPMC_A[0]_MUX0 */\
MUX_VAL(PINCNTL244, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[4]/EMAC[0]_RGRXD[3] */\
MUX_VAL(PINCNTL245, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[5]/EMAC[0]_RGTXD[3] */\
MUX_VAL(PINCNTL246, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[6]/EMAC[0]_RGTXD[2] */\
MUX_VAL(PINCNTL247, (IEN | IPD | FCN1 )) /* EMAC[0]_MRXD[7]/EMAC[0]_RGTXD[1] */\
MUX_VAL(PINCNTL248, (IEN | IPD | FCN5 )) /* GPMC_A[5]_MUX0 */\
MUX_VAL(PINCNTL249, (IEN | IPD | FCN5 )) /* GPMC_A[6]_MUX0 */\
MUX_VAL(PINCNTL250, (IEN | IPD | FCN5 )) /* GPMC_A[7]_MUX0 */\
MUX_VAL(PINCNTL251, (IEN | IPD | FCN5 )) /* GPMC_A[8]_MUX0 */\
MUX_VAL(PINCNTL252, (IEN | IPD | FCN5 )) /* GPMC_A[9]_MUX0 */\
MUX_VAL(PINCNTL253, (IEN | IPD | FCN5 )) /* GPMC_A[10]_MUX0 */\
MUX_VAL(PINCNTL254, (IEN | IPD | FCN5 )) /* GPMC_A[11]_MUX0 */\
MUX_VAL(PINCNTL255, (IEN | IPD | FCN5 )) /* GPMC_A[12]_MUX0 */\
MUX_VAL(PINCNTL256, (IEN | IPD | FCN5 )) /* GPMC_A[13]_MUX0 */\
MUX_VAL(PINCNTL257, (IEN | IPD | FCN5 )) /* GPMC_A[14]_MUX0 */\
MUX_VAL(PINCNTL258, (IEN | IPD | FCN5 )) /* GPMC_A[15]_MUX0 */\
MUX_VAL(PINCNTL259, (IEN | IPD | FCN8 )) /* GP3[31] */\
MUX_VAL(PINCNTL260, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL261, (IEN | IPU | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL262, (IEN | DIS | DISABLED )) /* safe_mode */\
MUX_VAL(PINCNTL263, (IEN | IPU | FCN1 )) /* I2C[0]_SCL */\
MUX_VAL(PINCNTL264, (IEN | IPU | FCN1 )) /* I2C[0]_SDA */\
MUX_VAL(PINCNTL270, (IEN | IPD | FCN1 )) /* USB0_DRVVBUS */

#endif