//------------------------------------------------------------------------------
//
//  Function:  InitializeUART
//
//  This function initializes a UART register.
//
static VOID InitializeUART(UARTPDD *pPdd)
{
    SOC_UART_REGS *pUartRegs = pPdd->pUartRegs;

    // Reset UART & wait until it completes
    OUTREG8(&pUartRegs->SYSC, UART_SYSC_RST);
    while ((INREG8(&pUartRegs->SYSS) & UART_SYSS_RST_DONE) == 0);

    // Enable wakeup
    // REG: turning off Auto Idle and turning on Smart Idle
    OUTREG8(
    &pUartRegs->SYSC,
    // Try turn on force idle, smart idle or turn on no idle
    // Lets configure force idle here we will change this in HWopen.
    UART_SYSC_IDLE_FORCE|UART_SYSC_WAKEUP_ENABLE|UART_SYSC_AUTOIDLE
    );

    // Ensure baud rate generator is off
    OUTREG8(&pUartRegs->LCR, UART_LCR_DLAB);
    OUTREG8(&pUartRegs->DLL, 0);
    OUTREG8(&pUartRegs->DLH, 0);

    // Select UART mode
    OUTREG8(&pUartRegs->MDR1, UART_MDR1_UART16);


    // Line control: configuration mode B
    OUTREG8(&pUartRegs->LCR, UART_LCR_MODE_CONFIG_B);
    // Enable access to IER bits 4-7, FCR bits 4-5 and MCR bits 5-7
    SETREG8(&pUartRegs->EFR, UART_EFR_ENHANCED_EN);

    // Line control: operational mode
    OUTREG8(&pUartRegs->LCR, UART_LCR_MODE_OPERATIONAL);

    // Enable sleep mode
    // Do not enable sleep mode hardware flow control will have problem
   // OUTREG8(&pUartRegs->IER, UART_IER_SLEEP_MODE);

    // Enable access to TCR and TLR
    SETREG8(&pUartRegs->MCR, UART_MCR_TCR_TLR);
    // Start receive when 32 bytes in FIFO, halt when 60 byte in FIFO
    OUTREG8(
        &pUartRegs->TCR,
        UART_TCR_RX_FIFO_TRIG_START_24|UART_TCR_RX_FIFO_TRIG_HALT_40
        );

    // This will create a space of 60 bytes in the FIFO for TX
    // Later we set FCR[4:5] so that the space is 63 bytes
    // we adjusted the TX DMA frame size to be 63 so we don't overrun our 
fifo
    if(pPdd->RxDmaInfo)
    {
        // if RxDMA is enabled, set up the MSBs of RX_FIFO_TRIG according
        // to the value in pPdd->dwRxFifoTriggerLevel
        BYTE    bRxTrigDMA = (BYTE)((pPdd->dwRxFifoTriggerLevel >> 2) << 4);

        OUTREG8(&pUartRegs->TLR, UART_TLR_TX_FIFO_TRIG_DMA_0 | bRxTrigDMA);
    }
    else
    {
//        OUTREG8(&pUartRegs->TLR, UART_TLR_TX_FIFO_TRIG_DMA_0);
        OUTREG8(&pUartRegs->TLR, (UCHAR)pPdd->dwTxBufIntr); //�@dwTxBufIntr=0x81
    }

    // Disable access to TCR and TLR
    CLRREG8(&pUartRegs->MCR, UART_MCR_TCR_TLR);

    pPdd->CurrentSCR = UART_SCR_TX_TRIG_GRANU1 | UART_SCR_RX_TRIG_GRANU1;
    pPdd->CurrentFCR = 0;

    if(pPdd->RxDmaInfo || pPdd->TxDmaInfo)
    {
        //pPdd->CurrentSCR |= UART_SCR_DMA_MODE_CTL;
        pPdd->CurrentSCR |=
                            UART_SCR_DMA_MODE_CTL |
                            UART_SCR_DMA_MODE_2_MODE1 |
                            UART_SCR_TX_EMPTY_CTL;
        pPdd->CurrentFCR |= UART_FCR_DMA_MODE;
    }

    OUTREG8(&pPdd->pUartRegs->SCR, pPdd->CurrentSCR);

    pPdd->intrMask = UART_IER_RHR;
    pPdd->CurrentFCR |= UART_FCR_FIFO_EN;  

    if (pPdd->RxDmaInfo == NULL)
    {
        pPdd->CurrentFCR |= UART_FCR_RX_FIFO_TRIG_8;
    }
    else
    {
        // if RxDMA is enabled, set up the LSBs of RX_FIFO_TRG according
        // to the value in pPdd->dwRxFifoTriggerLevel
        pPdd->CurrentFCR |= ((pPdd->dwRxFifoTriggerLevel & 0x03) << 6);
    }

    OUTREG8(&pUartRegs->FCR, pPdd->CurrentFCR);

    // Line control: configuration mode B
    OUTREG8(&pUartRegs->LCR, UART_LCR_MODE_CONFIG_B);
    // Disable access to IER bits 4-7, FCR bits 4-5 and MCR bits 5-7
    CLRREG8(&pUartRegs->EFR, UART_EFR_ENHANCED_EN);
    // Line control: operational mode
    OUTREG8(&pUartRegs->LCR, UART_LCR_MODE_OPERATIONAL);

    // Set default LCR 8 bits, 1 stop, no parity
    SETREG8(&pUartRegs->LCR, UART_LCR_CHAR_LENGTH_8BIT);
}