Changes in demo_vcap_venc_vdec_vdis.c
##########################################################################################


    /* Setup Vdis context */
    vdisParams.deviceParams[VDIS_DEV_HDMI].resolution = VSYS_STD_1080P_60;

//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
         vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_PAL;
//         vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution = VSYS_STD_1080P_60;
//<<
         /* If HDCOMP and DVO2 are tied together they must have same resolution */
        vdisParams.deviceParams[VDIS_DEV_DVO2].resolution = vdisParams.deviceParams[VDIS_DEV_HDCOMP].resolution;
        /* This call will set tiedDevicesMask internally in VDIS to tie HDCOMP and DVO2 together.
           This call will also set resolution for the tied vencs. Please note resolution for the tied vencs should be same. */
        Vdis_tiedVencInit(VDIS_DEV_HDCOMP, VDIS_DEV_DVO2, &vdisParams);

    vdisParams.deviceParams[VDIS_DEV_SD].resolution = VSYS_STD_PAL;





Changes in ti_vdis.c.c
##########################################################################################

 in Void Vdis_params_init(VDIS_PARAMS_S * pContext):



    pContext->tiedDevicesMask = VDIS_VENC_HDMI | VDIS_VENC_DVO2;
//20140519heb- Replaced SII9022 by SAA7129
//>>
//   pContext->enableConfigExtVideoEncoder = TRUE;
    pContext->enableConfigExtVideoEncoder = FALSE;
//<<

#if defined(TI814X_DVR) || defined(TI810X_DVR)
    pContext->enableConfigExtVideoEncoder = FALSE;
#endif

    pContext->deviceParams[VDIS_DEV_DVO2].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.vencNodeNum = VDIS_VENC_DVO2;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFidPolarity = VDIS_POLARITY_ACT_HIGH;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoVsPolarity = VDIS_POLARITY_ACT_HIGH;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoHsPolarity = VDIS_POLARITY_ACT_HIGH;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoActVidPolarity = VDIS_POLARITY_ACT_HIGH;
//20140519heb- Replaced SII9022 by SAA7129
//>>
//    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_DOUBLECHAN;
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dvoFmt = VDIS_DVOFMT_SINGLECHAN;
//<<
    pContext->deviceParams[VDIS_DEV_DVO2].outputInfo.dataFormat = SYSTEM_DF_YUV422SP_UV;

    pContext->deviceParams[VDIS_DEV_HDMI].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.vencNodeNum = VDIS_VENC_HDMI;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_EMBSYNC;
    pContext->deviceParams[VDIS_DEV_HDMI].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;

    pContext->deviceParams[VDIS_DEV_SD].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.vencNodeNum = VDIS_VENC_SD;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.aFmt = VDIS_A_OUTPUT_COMPOSITE;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_DISCSYNC;
    pContext->deviceParams[VDIS_DEV_SD].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;

#if defined(TI_816X_BUILD) || defined (TI_8107_BUILD)
    pContext->deviceParams[VDIS_DEV_HDCOMP].enable = TRUE;
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.vencNodeNum = VDIS_VENC_HDCOMP;
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.aFmt = VDIS_A_OUTPUT_COMPONENT;
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_EMBSYNC;
#if defined (TI_8107_BUILD)
    pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dvoFmt = VDIS_DVOFMT_TRIPLECHAN_DISCSYNC;
#endif
#if defined(TI816X_DVR) || defined(TI8107_DVR) || defined(TI8107_EVM)
        pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dataFormat = SYSTEM_DF_RGB24_888;
#endif
#if defined (TI816X_EVM)
        pContext->deviceParams[VDIS_DEV_HDCOMP].outputInfo.dataFormat = SYSTEM_DF_YUV444P;
#endif
    pContext->tiedDevicesMask = VDIS_VENC_HDCOMP | VDIS_VENC_DVO2;
    pContext->enableEdgeEnhancement = TRUE;

#endif





Changes in displayLink_drv.c
##########################################################################################

 in Int32 DisplayLink_drvDisplayCreate(DisplayLink_Obj * pObj):

    switch (pObj->tskId)
    {
        default:
        case SYSTEM_LINK_ID_DISPLAY_0:
            pObj->displayInstId = VPS_DISP_INST_BP0;
//20140519heb- Added / changed for HDCOMP / DVO2 interlaced mode
//>>
            pFormat->scanFormat = FVID2_SF_INTERLACED;
//            pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
//<<
            break;

        case SYSTEM_LINK_ID_DISPLAY_1:
            pObj->displayInstId = VPS_DISP_INST_BP1;
            pFormat->scanFormat = FVID2_SF_PROGRESSIVE;
            break;

        case SYSTEM_LINK_ID_DISPLAY_2:
            pObj->displayInstId = VPS_DISP_INST_SEC1;
            pFormat->scanFormat = FVID2_SF_INTERLACED;
            break;
    }





Changes in system_dctrl.c
##########################################################################################


Vps_DcConfig gSystem_dctrlTriDisplayConfigDvo2 = {
    VPS_DC_USERSETTINGS,                                   /* Use Case */
    /* Edge information */
    {
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//     {VPS_DC_BP0_INPUT_PATH, VPS_DC_VCOMP_MUX}     ,
     {VPS_DC_BP1_INPUT_PATH, VPS_DC_VCOMP_MUX}     ,
//<<
     {VPS_DC_VCOMP_MUX, VPS_DC_VCOMP}     ,
     {VPS_DC_CIG_NON_CONSTRAINED_OUTPUT, VPS_DC_HDMI_BLEND}     ,
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//     {VPS_DC_BP1_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
     {VPS_DC_BP0_INPUT_PATH, VPS_DC_HDCOMP_MUX}     ,
//<<
     {VPS_DC_HDCOMP_MUX, VPS_DC_CIG_PIP_INPUT}     ,
     {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_DVO2_BLEND}     ,
     {VPS_DC_CIG_PIP_OUTPUT, VPS_DC_HDCOMP_BLEND}     ,
     {VPS_DC_SEC1_INPUT_PATH, VPS_DC_SDVENC_MUX}     ,
     {VPS_DC_SDVENC_MUX, VPS_DC_SDVENC_BLEND}     ,
     {VPS_DC_GRPX0_INPUT_PATH, VPS_DC_HDMI_BLEND}     ,
     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_HDCOMP_BLEND}     ,
     {VPS_DC_GRPX1_INPUT_PATH, VPS_DC_DVO2_BLEND}
     }
    ,
    12,
    /* VENC information */
    {
     /* Mode information */
     {
      {VPS_DC_VENC_HDMI, {FVID2_STD_1080P_60}
       }
      ,                                                    /* 1080p30 is mode
                                                            * is overwritten
                                                            * later inside
                                                            * System_displayCtrlInit
                                                            */
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//      {VPS_DC_VENC_HDCOMP, {FVID2_STD_1080P_60}
      {VPS_DC_VENC_HDCOMP, {FVID2_STD_PAL}

//<<
       }
      ,                                                    /* 1080p30 is mode
                                                            * is overwritten
                                                            * later inside
                                                            * System_displayCtrlInit
                                                            */
//20140519heb- Changed for HDCOMP / DVO2 interlaced mode
//>>
//      {VPS_DC_VENC_DVO2, {FVID2_STD_1080P_60}
      {VPS_DC_VENC_DVO2, {FVID2_STD_PAL}

//<<
       }
      ,                                                    /* 1080p30 is mode
                                                            * is overwritten
                                                            * later inside
                                                            * System_displayCtrlInit
                                                            */
      {VPS_DC_VENC_SD, {FVID2_STD_NTSC}
       }
      }
     ,
     (VPS_DC_VENC_DVO2 | VPS_DC_VENC_HDCOMP),              /* Tied VENC bit
                                                            * mask */
     4u                                                    /* Number of VENCs
                                                            */
     }
};



Int32 System_getClk(UInt32 displayRes)
{
    Int32 clkValue = VSYS_STD_MAX;
    switch(displayRes) {
        case VSYS_STD_1080P_30:
        case VSYS_STD_1080I_60:
            clkValue = 74250u;
        break;
        case VSYS_STD_720P_60:
            clkValue = 74250;
        break;
        case VSYS_STD_1080P_60:
        case VSYS_STD_1080P_50:
            clkValue = 148500u;
        break;
        case VSYS_STD_XGA_60:
            clkValue = 65000u;
        break;
        case VSYS_STD_SXGA_60:
            clkValue = 108000u;
        break;
//20140519heb- Added for HDCOMP / DVO2 interlaced mode
//>>
        case VSYS_STD_PAL:
            clkValue = 27000u;
        break;
//<<
        
        default:
            UTILS_assert(0);
        break;
    }
    return(clkValue);
}