//ADC chip ADS5404 registers 		//SPI Data fromat: RW,A7-A0, D15-D0
	u32	RESET_REG = 0x2CD2F0;			//Addr: 0x2C,  	Data: 0b 1101 0010 1111 0000	// Reset code
	u32	TEMP_REG  = 0x2B0000;			//Addr: 0x2B,  	Data: 0b 0000 0000 0000 0000	// Read-only temperature

	u32	ADC_regs[] = {
						0x000000,			//Addr: 0x00,	Data: 0b 0000 0000 0000 0000
						//0x01820A,			//Addr: 0x01,	Data: 0b 1000 0010 0000 1010 // ch correction on
						0x01020A,			//Addr: 0x01,	Data: 0b 0000 0010 0000 1010 // ch correction chA off
						//0x01000A,			//Addr: 0x01,	Data: 0b 0000 0000 0000 1010 // ch correction chA&B off!
						0x020780,			//Addr: 0x02,  	Data: 0b 0000 0111 1000 0000
						0x034B18,			//Addr: 0x03,	Data: 0b 0100 1011 0001 1000	//DC Offset Corr ChA Clear
						0x0E0000,			//Addr: 0x0E,  	Data: 0b 0000 0000 0000 0000
						0x0F0030,			//Addr: 0x0F,  	Data: 0b 0000 0000 0011 0000
						0x1A4B18,			//Addr: 0x1A,  	Data: 0b 0100 1011 0001 1000	//DC Offset Corr ChB Clear
						//0x370000,			//Addr: 0x37,  	Data: 0b 0000 0000 0000 0000	// sleep-mode Complete Shutdown
						//0x378000,			//Addr: 0x37,  	Data: 0b 1000 0000 0000 0000	// sleep-mode Standby
						//0x37C000,			//Addr: 0x37,  	Data: 0b 1100 0000 0000 0000	// sleep-mode Deep sleep
						0x37D400,			//Addr: 0x37,  	Data: 0b 1101 0100 0000 0000	// sleep-mode Light sleep
						//0x38FFDF,			//Addr: 0x38,  	Data: 0b 1111 1111 1101 1111	// internal bias on
						0x38FF9F,			//Addr: 0x38,  	Data: 0b 1111 1111 1001 1111	// internal bias off
						//0x3A981B,			//Addr: 0x3A,  	Data: 0b 1001 1000 0001 1011
						0x3A0E08,			//Addr: 0x3A,  	Data: 0b 0000 1110 0000 1000
						0x660FFC,			//Addr: 0x66,	Data: 0b 0000 1111 1111 1100
						0x670FFF,			//Addr: 0x67,	Data: 0b 0000 1111 1111 1111
						0x3C0000,			//Addr: 0x3C,	test pattern off
						0x3D0000,			//Addr: 0x3D,	test pattern off
						0x3E0000,			//Addr: 0x3E,	test pattern off

						//0x030B18,			//Addr: 0x03,	Data: 0b 0000 1011 0001 1000	//DC Offset Corr ChA Enable
						0x1A0B18,			//Addr: 0x1A,  	Data: 0b 0000 1011 0001 1000	//DC Offset Corr ChB Enable
			}