Operating System Name : Windows 7 Enterprise 32 bit Service Pack 1
Error code : 102.000000
Error Description: 
Read DDR to file
TIMED_OUT_ERROR
Possible reasons for Time Out Error:     
1.FPGA may be in reset.
2.Clock from ADC EVM is not received by TSW Board. Please check if D4 LED is blinking.
3.SYNC is not established between ADC and FPGA. Please check if D3 LED is OFF. 
Possible reasons for SYNC Failure:               
a.JESD Ref clock Input Frequency to the TSW board from ADC EVM is not correct.  
b.JESD configuration is not same in ADC and the INI file selected.
ADC/DAC name : ADS54J69_2x_4222
IID: 3.000000
Device config details:

[ADC]

Interface name="TSW14J56REVD_FIRMWARE"
Number of channels=2
\\Channel Pattern=1-2,2-2,1-4,2-4,1-6,2-6,1-8,2-8,1-1,2-1,1-3,2-3,1-5,2-5,1-7,2-7
Channel Pattern=1-2,1-4,1-1,1-3,2-2,2-4,2-1,2-3,1-6,1-8,1-5,1-7,2-6,2-8,2-5,2-7
Data Postprocessing=1:32768
\\operation:operand
\\operaion
\\0=bit shift
\\1=xor
\\2=and
\\3=or
\\4=not
\\operand
\\value(+ve if bitshift by right and -ve if bitshift by left)
\\E.g 0:-2,1:1024
\\bitshift by left 2 times and then xor by 1024
Number of Bits=16
Max sample Rate=500000000
Register_Config="-"
\\[Register Address]:[Register Value]:[Number of Bytes to be sent as]
DLL Version=1.0
Read EVM Setup Procedure="EVM Setup Procedure not available"
\\use <> as delimiter for newline

[Version 1.0]

JESD IP Core_CS=0
JESD IP Core_F=2
JESD IP Core_HD=0
JESD IP Core_K=16
JESD IP Core_L=4
JESD IP Core_M=4
JESD IP Core_N=16
JESD IP Core_NTotal=16
JESD IP Core_S=1
JESD IP Core_SCR=0
JESD IP Core_Tailbits=0
JESD IP Core_LaneSync=1
JESD IP Core_Subclass=1
JESD IP Core_JESDV=1
MIF Config= 0.611G to 1.5G:RX:RX_PMA_x10,1.5G to 5.125G:RX:RX_PMA_x20
\\List of Lane Rate Range,PLL Type and their MIF File names that needs to be configured,separated by ":"
\\These MIF Files need to be present under MIF Files Folder
Fabric PLL Counter = 0.611G to 1.5G:0x080808,1.5G to 5.125G:0x080404
Invert Sync Polarity = 0 
\\Invert Sync polarity, 1:invert; 0: do not invert
Invert Serdes Data = 0  
\\Invert Serdes Data, 1:invert; 0: do not invert
Transceiver Mode = 0  
\\1:xcvr mode; 0: TX/RX only mode
Lane Mapping=lane0:7,lane1:4,lane2:3,lane3:0
\\Lane pattern for the LMF modes
Group 128 bits Flag = 1
\\If 1, will group 128 bits from each DDR, and then apply the channel pattern