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-- Company: 
-- Engineer: 
-- 
-- Create Date:    20:03:00 08/19/2017 
-- Design Name: 
-- Module Name:    Top_Dac - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity Top_Dac is
    Port (	CLK_50MHz 		: in  STD_LOGIC;  -- system clock
				-------------SPI singal declarations-------------
				SPI_SEL			: out std_logic;
				RESET				: out std_logic;
				SPI_SCK			: out std_logic;
				SPI_DIN			: in 	std_logic;
				SPI_DOUT			: out std_logic;
				SPI_LDAC			: out std_logic
--				-------------UART Interface----------------------
--				FPGA_UART_TX	: out std_logic;
--				FPGA_UART_RX	: in 	std_logic;
--				-------------LED Signal Declarations-------------
--				LED				: out std_logic_vector(7 downto 0)				
		);
end Top_Dac;

architecture Behavioral of Top_Dac is


component clk_40
	PORT
	(
		areset		: IN STD_LOGIC  := '0';
		inclk0		: IN STD_LOGIC  := '0';
		c0				: OUT STD_LOGIC ;
		locked		: OUT STD_LOGIC 
	);
end component;


	
	COMPONENT Reg_Data_Set
	PORT(
				clk		: IN std_logic;          
				rst 		: OUT std_logic;
				spi_en	: OUT std_logic;
				spi_data : OUT std_logic_vector(15 downto 0);
				spi_addr : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;
	
	COMPONENT DAC8775_SPI
		PORT	(
				clk			:	 IN STD_LOGIC;
				rst			:	 IN STD_LOGIC;
				en				:	 IN STD_LOGIC;
				spi_din		:	 IN STD_LOGIC;
				spi_clk		:	 OUT STD_LOGIC;
				spi_en		:	 OUT STD_LOGIC;
				ldac			: 	 OUT STD_LOGIC;
				spi_dout		:	 OUT STD_LOGIC;
				spi_addr		:	 IN STD_LOGIC_VECTOR(7 DOWNTO 0);
				spi_data		:	 IN STD_LOGIC_VECTOR(15 DOWNTO 0);
				spi_rd_data	:	 OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
				data_rdy		:	 OUT STD_LOGIC
				);
	END COMPONENT;

	
	--signal Clock_40MHz_wire : std_logic;
	--signal locked_wire		: std_logic;
	signal Reset_Reg_data	: std_logic;
	signal En_Reg_data		: std_logic;
	signal Data_Reg_data		: std_logic_vector(15 downto 0);
	signal address_Reg_data	: std_logic_vector(7 downto 0);	
	signal spi_rd_data		: std_logic_vector(15 downto 0);
	signal spi_data_rdy		: std_logic;
	signal spi_din_top		: std_logic;
	signal spi_clk_top		: std_logic;
	signal spi_en_top			: std_logic;
	signal spi_dout_top		: std_logic;
	signal locked_wire		: std_logic;
		signal clock_40		: std_logic;
Begin
clk_40_inst : clk_40 PORT MAP (
		areset	 => '0',
		inclk0	 => CLK_50MHz,
		c0	 => clock_40,
		locked	 => locked_wire
	);

	Inst_Reg_Data_Set: Reg_Data_Set PORT MAP(
										clk 		=> clock_40 ,
										rst 		=> Reset_Reg_data,
										spi_en 	=> En_Reg_data ,
										spi_data => Data_Reg_data,
										spi_addr => address_Reg_data
	);
								
	U2 : DAC8775_SPI port map (
										clk			=>	clock_40,										
										rst			=> Reset_Reg_data,
										en				=> En_Reg_data,
										spi_din		=> SPI_DIN,				--spi_din_top,
										spi_clk		=> SPI_SCK,				--spi_clk_top,
										spi_en		=> SPI_SEL,				--spi_en_top,
										ldac			=> SPI_LDAC,			--LDAC signal,
										spi_dout		=> SPI_DOUT,			--spi_dout_top,
										spi_addr		=> address_Reg_data,
										spi_data		=> Data_Reg_data,
										spi_rd_data	=> open,
										data_rdy		=> open
									 );
--
									RESET <= Reset_Reg_data	;			 
--SPI_DIN <= spi_dout_top;
--SPI_SCK <= spi_clk_top;
--SPI_SEL <= spi_en_top;
--SPI_DOUT<= spi_din_top;								
											
											
end Behavioral;