// 1 set the DAC sleep pin to low

	// 2 toggle the DAC RESETB pin to low and then high
	
	// 3 put JESD block in INIT state and reset jesd block
	DAC_WriteReg(0x4A,0x003e);// bit0:0 reset jesd block bit4-bit1:1111 put JESD block into INIT_STATE

	// set config 26,49,50,51 dac pll

	// DAC PLL and OUTPUT sleep
	DAC_WriteReg(0x1A,0x0003);// 0023 dac pll sleep
	// dac pll settings
	
	////////////////////////////////////////////
	DAC_WriteReg(0x31,0x0408);//n=1 lockdet_adj 000
	DAC_WriteReg(0x32,0x0130);//m=1,p=5
	///////////////////////////////////////////
	DAC_WriteReg(0x33,0x4da8);//600uA charge current

	// set config59,61,62  serdes pll

	// serdes settings
	DAC_WriteReg(0x3B,0x0800); //internal clock, div =1 means divide by 2
	DAC_WriteReg(0x3C,0x0028);  // VRANGE =0 MPY=5

	DAC_WriteReg(0x3D,0x0098);
 	DAC_WriteReg(0x3E,0x8128); //RATE:01(half)

	// set config63,71,73,74,96
	DAC_WriteReg(0x3F,0x00ff);
	DAC_WriteReg(0x46,0x10c0);// lane 0 ID :2  lane1 ID:3  lane2 ID:0
	DAC_WriteReg(0x47,0x090a);// lane 3 ID :1

	DAC_WriteReg(0x48,0x31c3);
	DAC_WriteReg(0x49,0x5550);
	DAC_WriteReg(0x4A,0x033f);// put JESD block into INIT state and reset it

	// set clkjesd_div,cdrvser_sysref_mode,interp registers
		//jesd clock div
	DAC_WriteReg(0x25,0x4000); 
	DAC_WriteReg(0x24,0x20);
	DAC_WriteReg(0x5c,0x02);

	DAC_WriteReg(0x00,0x0218);//4x
	
	//verify pll lock by alarm_rw0_pll and alarm_rw1_pll
	//  clear config108 alarms by write 0 to the register
	DAC_WriteReg(0x6c,0x0);
			// read cnofig108 make sure DAC PLL is locked and SERDES PLL locked
		do{
			 DAC_WriteReg(0x6c,0x0);

			 data = DAC_ReadReg(0x6c);
			 data = data & 0x0009;
		}while(data !=0x0);
	// set config3 ,config74-77,config79,80-85,config92,config97,


	DAC_WriteReg(0x02,0x2002);


	DAC_WriteReg(0x03,0xf300);
	DAC_WriteReg(0x4A,0x033f);// put JESD block into INIT state and reset it
		// JESD block settings
		///////////////////////////////////
	DAC_WriteReg(0x4B,0x1f01); //32 frame in multiframe configuration, 2 octets per frame per lane(222 configuration)
	DAC_WriteReg(0x4C,0x1f01);
	
		////////////////////////////////////
	DAC_WriteReg(0x4D,0x0100);
	DAC_WriteReg(0x4E,0x0F0F);
		//0x4f bit 5 no_lane_sync set1 to test CGS
		//DAC_WriteReg(0x4F,0x1c61);// ILA ignored
	DAC_WriteReg(0x4F,0x1cc1);//k28.0 1c

		// sync request generate for link0
	DAC_WriteReg(0x51,0x00dc);
	DAC_WriteReg(0x52,0x00ff);

		// sysref use all or one pulse skip
           DAC_WriteReg(0x5C,0x0002);

	// alarms signal
	DAC_WriteReg(0x04,0xFCFC);
	DAC_WriteReg(0x05,0xEFF0);
	// mask
	DAC_WriteReg(0x06,0xFCFC);//fcfc
	DAC_WriteReg(0x07,0x0000);
	// DAC PLL and OUTPUT sleep
	DAC_WriteReg(0x1A,0x0003);
	// atest and alarm output
	DAC_WriteReg(0x1B,0x1000);
	// sync select
	DAC_WriteReg(0x20,0x8008);
	// path in select
	DAC_WriteReg(0x22,0x1B1B);
	DAC_WriteReg(0x23,0x01FF);
	// octet path select
	DAC_WriteReg(0x5F,0x0123);
	DAC_WriteReg(0x60,0x4567);
	// sync pin select
	DAC_WriteReg(0x61,0x0010);// only sync_ab to fpga(link0)
	// below are flag registers
	DAC_WriteReg(0x2f,0x0004);
	DAC_WriteReg(0x30,0x0);

	//DAC_WriteReg(0x64,0x0000);
	DAC_WriteReg(0x65,0x0000);
	DAC_WriteReg(0x66,0x0000);
	DAC_WriteReg(0x67,0x0000);
	DAC_WriteReg(0x68,0x0000);
	DAC_WriteReg(0x69,0x0000);
	DAC_WriteReg(0x6A,0x0000);
	DAC_WriteReg(0x6B,0x0000);
	DAC_WriteReg(0x6C,0x0000);
	DAC_WriteReg(0x6D,0x0000);
	DAC_WriteReg(0x6E,0x0000);
	DAC_WriteReg(0x6F,0x0000);
	DAC_WriteReg(0x70,0x0000);
	DAC_WriteReg(0x71,0x0000);
	DAC_WriteReg(0x72,0x0000);
	DAC_WriteReg(0x73,0x0000);
	DAC_WriteReg(0x74,0x0000);
	DAC_WriteReg(0x75,0x0000);
	DAC_WriteReg(0x76,0x0000);
	DAC_WriteReg(0x77,0x0000);
	DAC_WriteReg(0x78,0x0000);
	DAC_WriteReg(0x79,0x0000);
	DAC_WriteReg(0x7A,0x0000);
	DAC_WriteReg(0x7B,0x0000);
	DAC_WriteReg(0x7C,0x0000);
	DAC_WriteReg(0x7D,0x0000);
	//   write config74 bit4-bit1 are all 0's (bring JESD out of INIT state)
 	DAC_WriteReg(0x4A,0x0320);

	//  write config 74 bit0 to 1(bring JESD out of reset state)
 	DAC_WriteReg(0x4A,0x0321);