//reading back all registers dac> read 1 Read 0xa70 from DAC address 0x1. dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xaa4 from DAC address 0x3. dac> read 4 Read 0x4000 from DAC address 0x4. dac> read 5 Read 0xf from DAC address 0x5. dac> read 6 Read 0x0 from DAC address 0x6. dac> read 9 Read 0xffff from DAC address 0x9. dac> read 0xe Read 0x0 from DAC address 0xe. // writing config registers //enable DAC dac> write 3 0x0a84 Wrote 0xa84 to DAC address 0x3. Read 0xa84 from DAC address 0x3. //check channel status is still off dac> read 9 Read 0xffff from DAC address 0x9. //turn off Broadcast for all channels dac> write 5 0x0 Wrote 0x0 to DAC address 0x5. Read 0x0 from DAC address 0x5. //reading key registers for status or any config register changes dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 2 Read 0x8 from DAC address 0x2. dac> read 9 Read 0xffff from DAC address 0x9. //set range to +/-12V dac> write 0xa 0xeeee Wrote 0xeeee to DAC address 0xa. Cannot readback this address (address is write only) //reading key registers for status or any config register changes dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xffff from DAC address 0x9. //enable all 4 channels dac> write 0x9 0xfff0 Wrote 0xfff0 to DAC address 0x9. Read 0xfff0 from DAC address 0x9. //AT THIS POINT ALL OUTPUTS GO TO AVSS -11V //reading key registers for status or any config register changes dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xfff0 from DAC address 0x9. //write into DAC channel 0 dac> write 0x10 0x8000 Wrote 0x8000 to DAC address 0x10. Cannot readback this address (address is write only) //OUTPUT STILL AT AVSS //reading key registers for status or any config register changes dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xfff0 from DAC address 0x9. //write into DAC channel 1 dac> write 0x11 0x8000 Cannot readback this address (address is write only) dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xfff0 from DAC address 0x9. //write into DAC channel 2 dac> write 0x12 0x8000 Wrote 0x8000 to DAC address 0x12. Cannot readback this address (address is write only) dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xfff0 from DAC address 0x9. //write into DAC channel 3 dac> write 0x13 0x8000 Wrote 0x8000 to DAC address 0x13. //enable broadcast mode dac> write 5 0xf Wrote 0xf to DAC address 0x5. Read 0xf from DAC address 0x5. dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xfff0 from DAC address 0x9. //write into broadacast reg. dac> write 0xf 0x0000 Wrote 0x0 to DAC address 0xf. Cannot readback this address (address is write only)' //OUTPUT STILL AT AVSS dac> write 0xf 0xffff Wrote 0xffff to DAC address 0xf. Cannot readback this address (address is write only) //OUTPUT CHANGES to AVDD dac> write 0xf 0x8000 Wrote 0x8000 to DAC address 0xf. Cannot readback this address (address is write only) //OUTPUT CHANGES to AVSS dac> read 2 Read 0x8 from DAC address 0x2. dac> read 3 Read 0xa84 from DAC address 0x3. dac> read 9 Read 0xfff0 from DAC address 0x9. dac> //issued soft reset to check condition of registers dac> write 0xe 0xa Wrote 0xa to DAC address 0xe. Read 0x0 from DAC address 0xe. dac> read 2 Read 0x8 from DAC address 0x2. //ALL OTHER INDERMEDIATE VALUES GIVE EITHER AVDD TO AVSS. THERE IS ONLY ONE UNIQUE CODE THAT THE OUTPUT FLOATS AND DRIFTS . THIS UNIQUE CODE CHANGES BASED ON DAC RANGE AND IS SLIGHTLY DIFFERENT FOR EACH POWER CYCLE