----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date:    16:44:27 05/10/2016 
-- Design Name: 
-- Module Name:    dac_sts - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
                use IEEE.STD_LOGIC_ARITH.ALL;
                use IEEE.STD_LOGIC_UNSIGNED.ALL;
                use IEEE.numeric_std.ALL;



-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity dac_sts is
    Port ( CLK_CRY : in  STD_LOGIC;
           DAC_SCLK,DAC_CLK : out  STD_LOGIC;
			 DAC_CS : OUT STD_LOGIC := '0';
			 GPIO_OUT : OUT STD_LOGIC_VECTOR(23 DOWNTO 0) ;
           DAC_SDIO : inout std_logic
           );
end dac_sts;

architecture Behavioral of dac_sts is

signal dac_count:  std_logic_vector(24 downto 0) := "0000000000000000000000000";
signal dac_cnt,dac_cot : integer range  0 to 95 := 0;
signal dac_delay : integer range 0 to 10000 := 0;
signal pn,pn1,pin : std_logic := '0';
signal dac_sclk_cntr : std_logic := '0';
SIGNAL adc_reg : STD_LOGIC_VECTOR(23 DOWNTO 0) := "000000000000000000000000"; 


begin

process(CLK_CRY) 
begin
		if rising_edge(CLK_CRY) then
			dac_count<= dac_count+ 1;
			dac_delay <= dac_delay + 1;
		end if;
				 DAC_CLK <= dac_count(1);
				 DAC_SCLK <= dac_count(4);
				 dac_sclk_cntr <= dac_count(4);
				 
		if dac_delay <= 1000 then
			DAC_SCLK <= '0';
			DAC_CLK <= '0';
		elsif dac_delay > 1000 then
		pn <= '1';
		end if;
		
end process;


process(CLK_CRY,dac_sclk_cntr)
begin
		if pn = '1' then
 
					if falling_edge(dac_sclk_cntr) then
									dac_cnt <= dac_cnt + 1;
					end if;
						 
		end if;
						if dac_cnt = 1 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 2 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 3 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 4 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 5 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 6 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 7 then
						DAC_SDIO <= '0';
												

						elsif dac_cnt = 8 then
						DAC_SDIO <= '1';
					-----------------------------------------------------------

						elsif dac_cnt = 9 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 10 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 11 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 12 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 13 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 14 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 15 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 16 then
						DAC_SDIO <= '0';
						------------------------------------

						elsif dac_cnt = 17 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 18 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 19 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 20 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 21 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 22 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 23 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 24 then
						DAC_SDIO <= '0';


----------************insr for dir************---------------
						elsif dac_cnt = 25 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 26 then						
						DAC_SDIO <= '1';

						elsif dac_cnt = 27 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 28 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 29 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 30 then
						DAC_SDIO <= '0';

						elsif dac_cnt = 31 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 32 then
						DAC_SDIO <= '0';

----------------------------------------------

						elsif dac_cnt = 33 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 34 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 35 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 36 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 37 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 38 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 39 then
						DAC_SDIO <= '1';

						elsif dac_cnt = 40 then
						DAC_SDIO <= '1';

						
						elsif dac_cnt = 41 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 42 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 43 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 44 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 45 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 46 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 47 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 48 then
						DAC_SDIO <=  '0';
						
						elsif dac_cnt = 49 then
						DAC_SDIO <=  '0';

						elsif dac_cnt = 50 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 51 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 52 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 53 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 54 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 55 then
						DAC_SDIO <=  '1';

						elsif dac_cnt = 56 then
						DAC_SDIO <=  '1';

						else
						DAC_SDIO <= '0'; 
--						pn <= '0';
						end if;				

end process;




end Behavioral;