omapdss MANAGER: omap_dss_mgr_apply(lcd)
omapdss CORE: restore context
omapdss CORE: save context
omapdss OVERLAY: check_overlay 0: (0,0 480x800 -> 480x800) disp (480x800)
omapdss MANAGER: omap_dss_mgr_apply(lcd)
omapdss OVERLAY: check_overlay 0: (0,0 480x800 -> 480x800) disp (480x800)
omapdss CORE: restore context
omapdss CORE: save context
omapdss MANAGER: omap_dss_mgr_apply(tv)
omapdss CORE: restore context
omapdss CORE: save context
omapdss DSI: dsi_display_enable
omapdss CORE: restore context
omapdss DISPC: xres 0 yres 0
omapdss DISPC: pck 0
omapdss DISPC: hsw 1 hfp 1 hbp 1 vsw 1 vfp 0 vbp 0
omapdss DISPC: hsync 0Hz, vsync 0Hz
DSI resets: PLL (0) CIO (0) PHY (0, 0, 0, 0)
omapdss DSI: PLL init
omapdss DSI: PLL init done
cinfo->clkin          =13000000
cinfo->highfreq       =0
cinfo->fint           =1000000
cinfo->clkin4ddr      =720000000
cinfo->dsi1_pll_fclk  =120000000
cinfo->dsi2_pll_fclk  =120000000
omapdss DSI: dsi_pll_set_clock_div()
omapdss DSI: DSI Fint 1000000
omapdss DSI: clkin (dss2_fck) rate 13000000, highfreq 0
omapdss DSI: CLKIN4DDR = 2 * 360 / 13 * 13000000 / 1 = 720000000
omapdss DSI: Data rate on 1 DSI lane 360 Mbps
omapdss DSI: Clock lane freq 180000000 Hz
omapdss DSI: regm3 = 6, dsi1_pll_fclk = 120000000
omapdss DSI: regm4 = 6, dsi2_pll_fclk = 120000000
omapdss DSI: PLL config done
omapdss DSI: PLL OK
omapdss DISPC: lck = 120000000 (1)
omapdss DISPC: pck = 30000000 (4)
omapdss DSI: dsi_complexio_init
omapdss DSI: ths_prepare 15 (83ns), ths_prepare_ths_zero 34 (188ns)
omapdss DSI: ths_trail 16 (88ns), ths_exit 27 (150ns)
omapdss DSI: tlpx_half 5 (27ns), tclk_trail 13 (72ns), tclk_zero 47 (261ns)
omapdss DSI: tclk_prepare 12 (66ns)
omapdss DSI: dsi_if_enable(1)
omapdss DSI: dsi_if_enable(0)
omapdss DSI: dsi_if_enable(1)
omapdss DSI: dsi_if_enable(0)
omapdss DSI: CIO init done
DSI resets: PLL (1) CIO (1) PHY (1, 1, 1, 1)
omapdss DSI: ddr_clk_pre 23, ddr_clk_post 16
omapdss DSI: enter_hs_mode_lat 14, exit_hs_mode_lat 14
omapdss DSI: LP_CLK_DIV 8, LP_CLK 7500000
DSI resets: PLL (1) CIO (1) PHY (1, 1, 1, 1)
omapdss DSI: STOP_STATE_COUNTER 4096 ticks (0x1000) = 34133 ns
omapdss DSI: TA_TO 1048448 ticks (0x1fff x8 x16) = 8737066 ns
omapdss DSI: LP_RX_TO 524224 ticks (0x1fff x4 x16) = 4368533 ns
omapdss DSI: HS_TX_TO 524224 ticks (0x1fff x4 x16) = 11649422 ns
omapdss DSI: dsi_vc_initial_config(0)
omapdss DSI: dsi_vc_initial_config(1)
omapdss DSI: dsi_vc_initial_config(2)
omapdss DSI: dsi_vc_initial_config(3)
omapdss DSI: dsi_vc_enable channel 0, enable 1
omapdss DSI: dsi_vc_enable channel 1, enable 1
omapdss DSI: dsi_vc_enable channel 2, enable 1
omapdss DSI: dsi_vc_enable channel 3, enable 1
omapdss DSI: dsi_if_enable(1)
mmc0: host does not support reading read-only switch. assuming write-enable.
omapdss DSI: dsi_vc_enable_hs(0, 0)
omapdss DSI: dsi_vc_enable channel 0, enable 0
omapdss DSI: dsi_if_enable(0)
omapdss DSI: dsi_vc_enable channel 0, enable 1
omapdss DSI: dsi_if_enable(1)
dsi_vc_send_short(ch1, dt 0x37, b1 0x3, b2 0x0)
omapdss DSI error: DSI CIO error, cio irqstatus 200000
DSI CIO IRQ 0x200000: ERRCONTENTIONLP1_1 
dsi_vc_send_short(ch0, dt 0x6, b1 0x4, b2 0x0)
omapdss DSI error: DSI CIO error, cio irqstatus 200000
DSI CIO IRQ 0x200000: ERRCONTENTIONLP1_1 
omapdss DSI error: DSI CIO error, cio irqstatus 200000
DSI CIO IRQ 0x200000: ERRCONTENTIONLP1_1 
mmc0: new SDHC card at address b368
omapdss DSI error: DSI error, irqstatus 100000
DSI IRQ: 0x100000: TA_TIMEOUT 
omapdss DSI error: Failed to receive BTA
omapdss DSI error: dsi_vc_dcs_read(ch 0, cmd 0x04) failed
config LCD dsi
omapdss DSI: dsi_vc_enable_hs(0, 1)
omapdss DSI: dsi_vc_enable channel 0, enable 0
omapdss DSI: dsi_if_enable(0)
omapdss DSI: dsi_vc_enable channel 0, enable 1
omapdss DSI: dsi_if_enable(1)