// Compare regs before-and-after // CM_PER_GPMC_CLKCTRL: // -> 0x3 // Writing 3 (RESERVED) to CM_PER_GPMC_CLKCTRL (by code and with CCS) always reads back 2. // OK? Before: CM_PER_GPMC_CLKCTRL = 00000002 Control the way mandatory clocks are managed. 0x2 = ENABLE : Module is explicitly enabled. Interface clock (if not used for functions) may be gated according to the clock domain state. Functional clocks are guarantied to stay present. As long as in this configuration, power domain sleep transition cannot happen. After: CM_PER_GPMC_CLKCTRL = 00000002 CM_PER_L3S_CLKSTCTRL: // write a -> 2, then transition to a final -> 0 // Code writes 0x2, waits for 0x2, then writes 0x0. // OK. // Before: CM_PER_L3S_CLKSTCTRL = 0000000A [3] CLKACTIVITY_L3S_GCLK = 1b This field indicates the state of the L3S_GCLK clock in the domain. 0x1 = Act [1-0] CLKTRCTRL = 10b 0x2 = SW_WKUP : SW_WKUP: Start a software forced wake-up transition on the domain. After: CM_PER_L3S_CLKSTCTRL = 00000008 [3] CLKACTIVITY_L3S_GCLK = 1b This field indicates the state of the L3S_GCLK clock in the domain. 0x1 = Act [1-0] CLKTRCTRL = 00b 0x0 = NO_SLEEP : NO_SLEEP: Sleep transition cannot be initiated. Wakeup transition may however occur. GPMC_GPMC_SYSCONFIG: // -> make sure Auto-idle is off and sidle=noidle // (0<<0)&GPMC_SYSCONFIG_AUTOIDLE | (1<<3)&GPMC_SYSCONFIG_IDLEMODE // GPMC_SYSCONFIG_AUTOIDLE?? assume this is a bit-field mask, 0x1<<0 // GPMC_SYSCONFIG_IDLEMODE?? assume this is a bit-field mask, 0x3<<3 // Before: GPMC_SYSCONFIG = 00000000 [4-3] SIDLEMODE = 00b Idle mode 0h = Force-idle. An idle request is acknowledged unconditionally [0] AUTOIDLE = 0b Internal OCP clock gating strategy. 0h = Interface clock is free-running After: GPMC_SYSCONFIG = 00000008 [4-3] SIDLEMODE = 01b Idle mode 1h = No-idle. An idle request is never acknowledged [0] AUTOIDLE = 0b Internal OCP clock gating strategy. 0h = Interface clock is free-running