// SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2024-2025 iwave Global Technologies Pvt Ltd. */ /dts-v1/; #include "k3-j7200-iwg52m.dtsi" #include #include #include #include #include / { chosen { stdout-path = "serial2:115200n8"; bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000"; }; aliases { i2c0 = &wkup_i2c0; i2c1 = &mcu_i2c0; ethernet0 = &cpsw0_port3; ethernet1 = &cpsw0_port2; ethernet2 = &cpsw0_port1; }; vdd_sd_dv: gpio-regulator-TLV71033 { /* Output of TLV71033 */ compatible = "regulator-gpio"; regulator-name = "tlv71033"; pinctrl-names = "default"; pinctrl-0 = <&vdd_sd_dv_pins_default>; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-boot-on; gpios = <&wkup_gpio0 84 0>; gpios-states = <0>; states = <1800000 0x1>, <3300000 0x0>; }; iwg52m_info { compatible = "iwave,iwg52m-info"; }; }; &wkup_pmx0 { b7_pins_default: b7-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8, PIN_OUTPUT, 2) /* (B7)*/ >; }; som_eeprom_pins_default: som-eeprom-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x24, PIN_INPUT, 7) /*A8 eeprom write protect gpio for Som*/ >; }; VU9p_pins_default_prog_pins_default: VU9p-pins-default-prog-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x28, PIN_OUTPUT, 7) /*WKUP_GPIO0_26*/ >; }; }; &wkup_pmx1 { d5_pins_default: d5-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x4, PIN_OUTPUT, 7) /* (D5)*/ >; }; }; &wkup_pmx2 { mcu_uart0_pins_default: mcu-uart0-default-pins { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x8c, PIN_INPUT, 0) /* (D20) MCU_UART0_RXD */ J721E_WKUP_IOPAD(0x88, PIN_OUTPUT, 0) /* (D19) MCU_UART0_TXD */ >; }; spi_pins_default: spi-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x58, PIN_INPUT, 0) /* (B18) WKUP_GPIO0_0.MCU_SPI1_CLK */ J721E_WKUP_IOPAD(0x5c, PIN_OUTPUT, 0) /* (B19) WKUP_GPIO0_1.MCU_SPI1_D0 */ J721E_WKUP_IOPAD(0x60, PIN_INPUT, 1) /* (D14) WKUP_GPIO0_2.MCU_SPI1_D1 */ J721E_WKUP_IOPAD(0x06c, PIN_OUTPUT, 2) /* (B16) WKUP_GPIO0_5 TPM CS*/ >; }; vu_pmic2_pins_default: vu-pmic2-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x54, PIN_INPUT, 7) /*A17*/ >; }; ps_gpio_header_uart_pins_default: ps-gpio-header-uart-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x90, PIN_INPUT, 7) /*E20*/ J721E_WKUP_IOPAD(0x94, PIN_INPUT, 7) /*E21*/ >; }; }; &wkup_pmx3 { vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x1C, PIN_OUTPUT, 7) /*E18 */ >; }; }; &main_pmx0 { main_uart0_pins_default: main-uart0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xb0, PIN_INPUT, 0) /* (T16) UART0_RXD */ J721E_IOPAD(0xb4, PIN_OUTPUT, 0) /* (T17) UART0_TXD */ >; }; VU9p_pins_default_done: VU9p-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd8, PIN_INPUT, 7) /* (W2) MAIN_GPIO0_57 */ >; }; main_mmc1_pins_default: main-mmc1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x104, PIN_INPUT, 0) /* (M20) MMC1_CMD */ J721E_IOPAD(0x100, PIN_OUTPUT, 0) /* (P21) MMC1_CLK */ J721E_IOPAD(0xfc, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */ J721E_IOPAD(0xf8, PIN_INPUT, 0) /* (M19) MMC1_DAT0 */ J721E_IOPAD(0xf4, PIN_INPUT, 0) /* (N21) MMC1_DAT1 */ J721E_IOPAD(0xf0, PIN_INPUT, 0) /* (N20) MMC1_DAT2 */ J721E_IOPAD(0xec, PIN_INPUT, 0) /* (N19) MMC1_DAT3 */ J721E_IOPAD(0xe4, PIN_INPUT, 8) /* (V1) TIMER_IO0.MMC1_SDCD */ >; }; main_cpsw_pins_default: main-cpsw-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x4c, PIN_INPUT, 4) /* (V19) MCAN5_RX.RGMII3_RD0 */ J721E_IOPAD(0x50, PIN_INPUT, 4) /* (T13) MCAN6_TX.RGMII3_RD1 */ J721E_IOPAD(0x54, PIN_INPUT, 4) /* (U14) MCAN6_RX.RGMII3_RD2 */ J721E_IOPAD(0x58, PIN_INPUT, 4) /* (U16) MCAN7_TX.RGMII3_RD3 */ J721E_IOPAD(0x48, PIN_INPUT, 4) /* (V21) MCAN5_TX.RGMII3_RXC */ J721E_IOPAD(0x5c, PIN_INPUT, 4) /* (U15) MCAN7_RX.RGMII3_RX_CTL */ J721E_IOPAD(0x60, PIN_OUTPUT, 4) /* (T15) MCAN8_TX.RGMII3_TD0 */ J721E_IOPAD(0x64, PIN_OUTPUT, 4) /* (U19) MCAN8_RX.RGMII3_TD1 */ J721E_IOPAD(0x68, PIN_OUTPUT, 4) /* (T14) MCAN9_TX.RGMII3_TD2 */ J721E_IOPAD(0x6c, PIN_OUTPUT, 4) /* (U18) MCAN9_RX.RGMII3_TD3 */ J721E_IOPAD(0x74, PIN_OUTPUT, 4) /* (U20) MCAN10_RX.RGMII3_TXC */ J721E_IOPAD(0x70, PIN_OUTPUT, 4) /* (U17) MCAN10_TX.RGMII3_TX_CTL */ >; }; main_mdio_pins_default: main-mdio1-pins-default{ pinctrl-single,pins = < J721E_IOPAD(0xa8, PIN_OUTPUT, 5) /* (W19) UART8_TXD.MDIO0_MDC */ J721E_IOPAD(0xa4, PIN_INPUT, 5) /* (W14) UART8_RXD.MDIO0_MDIO */ >; }; eth_reset_pins_default: gpio0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xd4, PIN_INPUT, 7) /* (V3) I2C0_SCL.GPIO0_56 */ >; }; Eth_10G_reset_pins_default: Eth-10G-reset-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xE0, PIN_INPUT, 7) /* (T3)*/ >; }; typec_irq_pins_default: typec-irq-pins-default { pinctrl-single,pins = < J721E_IOPAD(0xc4, PIN_INPUT_PULLUP, 7) /* (U5) MAIN_GPIO0_52 */ >; }; vu_pmic1_pins_default: vu-pmic1-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x1c, PIN_OUTPUT, 7) /*AA19*/ >; }; RGMII2_pins_default: RGMII2-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x28, PIN_OUTPUT, 4) /*(W21) RGMII2_TXC/MCAN1_TX/RMII2_TX_EN/SPI6_CS0/EHRPWM_SOCA/GPMC0_A3/MCASP0_AXR11/GPIO0_11*/ J721E_IOPAD(0xa0, PIN_OUTPUT, 4) /*(U21) RGMII2_TX_CTL/GPIO0_41/RMII2_TXD0/SPI6_D1/UART4_RXD/GPMC0_A13/MCASP2_ACLKX */ J721E_IOPAD(0x90, PIN_OUTPUT, 4) /*(W17) RGMII2_TD0/MCAN15_TX/RMII2_RXD0/GPIO0_37/SPI6_CS2/EQEP1_S/GPMC0_CSN2/GPMC0_A0/GPMC0_A21/MCASP2_AXR1*/ J721E_IOPAD(0x94, PIN_OUTPUT, 4) /*(W20) RGMII2_TD1/MCAN15_RX/RMII2_RXD1/SPI6_CS3/EQEP1_I/GPMC0_A15/GPMC0_ADVN_ALE/GPIO0_38/MCASP2_AXR2 */ J721E_IOPAD(0x98, PIN_OUTPUT, 4) /*(V14) RGMII2_TD2/UART2_RXD/RMII2_CRS_DV/SPI6_CLK/GPMC0_CLKOUT/GPMC0_FCLK_MUX/OBSCLK2/GPIO0_39/MCASP2_AXR3*/ J721E_IOPAD(0x9c, PIN_OUTPUT, 4) /*(V13) RGMII2_TD3/UART2_TXD/RMII2_RX_ER/GPIO0_40/SPI6_D0/MCASP2_AFSX */ J721E_IOPAD(0x78, PIN_INPUT, 4) /*(Y14) RGMII2_RXC/MCAN11_TX/SPI2_CS0/EQEP0_A/SPI0_CS2/UART3_RXD/MCASP0_AXR13/GPMC0_A11/UART0_DTRN/GPIO0_31*/ J721E_IOPAD(0x8c, PIN_INPUT, 4) /*(AA16) RGMII2_RX_CTL/MCAN13_RX/GPMC0_CSN3/GPIO0_36/SPI2_D1/EQEP0_I/I2C5_SDA/UART8_RTSN/I3C0_SDA/GPMC0_A20/MCASP2_AXR0 */ J721E_IOPAD(0x7c, PIN_INPUT, 4) /*(Y13) RGMII2_RD0/MCAN11_RX/SPI2_CS1/EQEP0_B/UART3_TXD/MCASP0_AXR14/GPMC0_A12/UART0_RIN/GPIO0_32 */ J721E_IOPAD(0x80, PIN_INPUT, 4) /*(AA15) RGMII2_RD1/GPIO0_33/SPI2_CS2/EQEP1_A/I2C6_SCL/UART2_RXD/MCASP0_AXR15/GPMC0_BE1N/GPMC0_A17/MCAN12_TX */ J721E_IOPAD(0x84, PIN_INPUT, 4) /*(AA14) RGMII2_RD2/GPIO0_34/SPI2_CS3/EQEP1_B/I2C6_SDA/UART2_TXD/MCASP1_AXR8/I3C0_SDAPULLEN/GPMC0_A18/MCAN12_RX */ J721E_IOPAD(0x88, PIN_INPUT, 4) /*(AA18) RGMII2_RD3/MCAN13_TX/GPMC0_WPN/SPI2_D0/EQEP0_S/I2C5_SCL/UART8_CTSN/MCASP1_AXR9/I3C0_SCL/GPMC0_A19/GPIO0_35 */ >; }; main_uart1_pins_default: main-uart1-default-pins { pinctrl-single,pins = < J721E_IOPAD(0xbc, PIN_OUTPUT, 0) /* (T20) UART1_TXD.MCAN17_RX */ J721E_IOPAD(0xb8, PIN_INPUT, 0) /* (T18) UART1_RXD.MCAN17_TX */ >; }; pcie_rst_pins_default: pcie-rst-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x44, PIN_OUTPUT, 7) /*Y20*/ >; }; ps_gpio_header_pins_default: ps-gpio-header-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x20, PIN_INPUT, 7) /* (V18) MCAN0_TX.GPIO0_9 */ J721E_IOPAD(0x24, PIN_INPUT, 7) /* (V20) MCAN0_RX.GPIO0_10 */ J721E_IOPAD(0x38, PIN_INPUT, 7) /* (Y21) MCAN3_TX.GPIO0_15 */ J721E_IOPAD(0x3c, PIN_INPUT, 7) /* (W16) MCAN3_RX.GPIO0_16 */ >; }; tpm_reset_pins_default: tpm-reset-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0c0, PIN_OUTPUT_PULLUP, 7) >; }; }; &main_pmx2 { main_usbss0_pins_default: main-usbss0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */ >; }; }; &mcu_uart0 { status = "okay"; /* Default pinmux */ pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { status = "okay"; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; pinctrl-names = "default"; pinctrl-0 = <&main_uart0_pins_default>; }; &main_uart1 { status = "okay"; /* Default pinmux */ pinctrl-names = "default"; pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { /* MAIN UART 2 is used by R5F firmware */ status = "reserved"; }; &main_gpio0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <ð_reset_pins_default &Eth_10G_reset_pins_default &ps_gpio_header_pins_default &VU9p_pins_default_done &tpm_reset_pins_default>; 10G_reset_gpio { gpio-hog; gpios = <59 GPIO_ACTIVE_HIGH>; output-high; linename = "10G_rst"; }; }; &main_gpio2 { status = "disabled"; }; &main_gpio4 { status = "disabled"; }; &main_gpio6 { status = "disabled"; }; &wkup_gpio0 { pinctrl-names = "default"; pinctrl-0 = <&ps_gpio_header_uart_pins_default &VU9p_pins_default_prog_pins_default>; }; &wkup_gpio1 { status = "disabled"; }; &cpsw0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_cpsw_pins_default &RGMII2_pins_default>; }; &davinci_mdio{ status = "disabled"; }; &mcu_cpsw{ status = "disabled"; }; &cpsw_port1 { status = "disabled"; }; &cpsw5g_mdio { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&main_mdio_pins_default>; phy3: ethernet-phy@3 { reg = <3>; compatible = "ethernet-phy-ieee802.3-c22"; }; phy1: ethernet-phy@1 { reg = <1>; compatible = "ethernet-phy-ieee802.3-c45"; }; }; &cpsw0_port3 { status = "okay"; pinctrl-names = "default"; phy-mode = "rgmii-id"; phy-handle = <&phy3>; phys = <&cpsw0_phy_gmii_sel 3>; }; &cpsw0_port1 { status = "okay"; phy-mode = "usxgmii"; phys = <&cpsw0_phy_gmii_sel 1>, <&serdes0_usxgmii_link>; phy-names = "mac", "serdes"; phy-handle = <&phy1>; }; &cpsw0_port2 { status = "okay"; phy-mode = "rgmii"; phys = <&cpsw0_phy_gmii_sel 2>; fixed-link { speed = <1000>; full-duplex; }; }; &main_i2c0 { status = "disabled"; }; &wkup_i2c0 { status = "okay"; clock-frequency = <400000>; eeprom_osm: eeprom@54 { status = "okay"; compatible = "atmel,24mac402"; reg = <0x54>; pagesize = <16>; address-width = <8>; size = <256>; }; i2c_mux: msd9548@73 { compatible = "nxp,pca9548"; reg = <0x73>; status = "okay"; #address-cells = <1>; #size-cells = <0>; i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1{ #address-cells = <1>; #size-cells = <0>; reg = <1>; ioexp3gpio: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; #gpio-cells = <2>; gpio-controller; #interrupt-cells = <2>; interrupt-controller; interrupt-parent = <&ioexp2gpio>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; label = "ioexp3gpio"; usb_power{ gpio-hog; gpios = <12 GPIO_ACTIVE_HIGH>; output-high; }; }; }; i2c@2 { #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { #address-cells = <1>; #size-cells = <0>; reg = <7>; ioexp1gpio: gpio@21 { compatible = "ti,tca6416"; reg = <0x21>; #gpio-cells = <2>; gpio-controller; interrupt-controller; #interrupt-cells = <2>; interrupt-parent = <&main_gpio0>; interrupts = <52 IRQ_TYPE_EDGE_FALLING>; label = "ioexp1gpio"; qsfp_1_top { gpio-hog; gpios = <0 0>; output-low; }; qsfp_1_bottom { gpio-hog; gpios = <5 0>; output-low; }; }; ioexp2gpio: gpio@20 { compatible = "ti,tca6416"; reg = <0x20>; #gpio-cells = <2>; gpio-controller; interrupt-parent = <&ioexp1gpio>; interrupt-controller; #interrupt-cells = <2>; interrupts = <15 IRQ_TYPE_EDGE_FALLING>; label = "ioexp2gpio"; qsfp_2_top { gpio-hog; gpios = <0 0>; output-low; }; qsfp_2_bottom { gpio-hog; gpios = <5 0>; output-low; }; }; fusb302: typec-portc@22 { compatible = "fcs,fusb302"; pinctrl-names = "default"; pinctrl-0 = <&typec_irq_pins_default>; reg = <0x22>; fcs,int_n = <&ioexp3gpio 15 IRQ_TYPE_EDGE_FALLING>; status = "okay"; }; dp159: hdmi-retimer@5b { status = "okay"; compatible = "ti,dp159"; reg = <0x5b>; #address-cells = <1>; #size-cells = <0>; #clock-cells = <0>; }; }; }; }; &mcu_i2c0 { status = "okay"; clock-frequency = <400000>; tmp442@4c { compatible = "ti,tmp442"; reg = <0x4c>; }; eeprom_som: eeprom@52 { pinctrl-names = "default"; pinctrl-0 = <&som_eeprom_pins_default>; status = "okay"; compatible = "atmel,24mac402"; reg = <0x52>; pagesize = <16>; address-width = <8>; size = <256>; }; eeprom_Carrier_board: eeprom@50 { compatible = "atmel,24c04"; reg = <0x50>; pagesize = <16>; address-width = <8>; size = <512>; }; vu09_pmic_1: vu09_da9062@48 { compatible = "dlg,da9062"; pinctrl-names = "default"; pinctrl-0 = <&vu_pmic1_pins_default>; reg = <0x48>; gpio-controller; #gpio-cells = <2>; status = "okay"; gpio { compatible = "dlg,da9062-gpio"; }; }; vu09_pmic_2: vu09_da9062@58 { compatible = "dlg,da9062"; pinctrl-names = "default"; pinctrl-0 = <&vu_pmic2_pins_default>; reg = <0x58>; gpio-controller; #gpio-cells = <2>; status = "okay"; gpio { compatible = "dlg,da9062-gpio"; }; }; }; &mcu_i2c1 { status = "disabled"; }; &main_sdhci0 { status = "okay"; /* eMMC */ non-removable; ti,driver-strength-ohm = <50>; disable-wp; }; &main_sdhci1 { status = "okay"; /* SD card */ pinctrl-0 = <&main_mmc1_pins_default>; pinctrl-names = "default"; vqmmc-supply = <&vdd_sd_dv>; ti,driver-strength-ohm = <50>; disable-wp; bus-width = <4>; }; &serdes_ln_ctrl { status = "okay"; idle-states = , , , ; }; &usb_serdes_mux { idle-states = <1>; /* USB0 to SERDES lane 3 */ }; &usbss0 { pinctrl-names = "default"; pinctrl-0 = <&main_usbss0_pins_default>; ti,vbus-divider; ti,usb2-only; }; &usb0 { status = "okay"; dr_mode = "host"; phy-names = "cdns3,usb2-phy"; }; &tscadc0 { adc { ti,adc-channels = <0 1 2 3 4 5 6 7>; }; }; &serdes_refclk { clock-frequency = <100000000>; }; &serdes_wiz0 { status = "okay"; }; &serdes0 { status = "okay"; serdes0_pcie_link: phy@0 { reg = <0>; cdns,num-lanes = <2>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; }; serdes0_usxgmii_link: phy@2 { reg = <2>; cdns,num-lanes = <1>; #phy-cells = <0>; cdns,phy-type = ; resets = <&serdes_wiz0 3>; }; }; &pcie1_rc { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&pcie_rst_pins_default>; reset-gpios = <&main_gpio0 18 GPIO_ACTIVE_HIGH>; phys = <&serdes0_pcie_link>; phy-names = "pcie-phy"; num-lanes = <2>; }; #define K3_TS_OFFSET(pa, val) (0x4+(pa)*4) (0x10000 | val) ×ync_router { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_cpsw_cpts>; /* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */ mcu_cpsw_cpts: mcu-cpsw-cpts { pinctrl-single,pins = < /* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */ K3_TS_OFFSET(25, 17) >; }; }; &mcu_spi1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi_pins_default>; ti,spi-num-cs = <4>; ti,pindir-d0-out-d1-in; tpm@3 { compatible = "tcg,tpm_tis-spi"; reg = <3>; spi-max-frequency = <16000000>; lpcpd-gpios = <&main_gpio0 51 GPIO_ACTIVE_HIGH>; status = "okay"; }; };