root@21ca7013e986:/home/root/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/c7x-mma-tidl/ti_dl/test# ./PC_dsp_test_dl_algo.out ----tidlMain-----797---------- ----tidlMain-----810---------- ----tidlMain-----851---------- ----tidlMain-----869---------- ----tidlMain-----884---------- ----tidlMultiInstanceTest-----268---------- ----tidlMultiInstanceTest-----304---------- Processing config file #0 : testvecs/config/infer/public/caffe/tidl_infer_mobilenetV1.txt ----tidlMultiInstanceTest-----383---------- ----tidlMultiInstanceTest-----408------:testvecs/config/tidl_models/caffe/tidl_io_mobilenet_v1_1.bin---- ----tidlMultiInstanceTest-----414---------- ----tidlMultiInstanceTest-----496---------- ----tidlMultiInstanceTest-----516---------- ----tidlMultiInstanceTest-----537---------- ---------1016---------- ----TIDLRT_create-----1043---------- ----TIDLRT_create-----1045---------- ----TIDLRT_create-----1077---------- ----TIDLRT_create-----1088---------- ----TIDLRT_create-----1091---------- ----TIDLRT_create-----1093---------- TIDL_initDebugTraceParams Done -------------------------------------------- TIDL Memory size requiement (record wise): MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr 0 , DDR Cacheable , Persistent , 128, 15.25 , 0x00000000 1 , DDR Cacheable , Persistent , 128, 0.64 , 0x00000000 2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000 3 , DDR Cacheable , Scratch , 128, 448.00 , 0x00000000 4 , DDR Cacheable , Scratch , 128, 2944.00 , 0x00000000 5 , DDR Cacheable , Persistent , 128, 4743.91 , 0x00000000 6 , DDR Cacheable , Scratch , 128, 7.75 , 0x00000000 7 , DDR Cacheable , Scratch , 128, 148.25 , 0x00000000 8 , DDR Cacheable , Scratch , 128, 4728.12 , 0x00000000 9 , DDR Cacheable , Scratch , 128, 1579.00 , 0x00000000 10 , DDR Cacheable , Persistent , 128, 447.48 , 0x00000000 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x00000000 12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000 13 , DDR Cacheable , Persistent , 128, 7069.64 , 0x00000000 14 , DDR Cacheable , Persistent , 128, 0.03 , 0x00000000 -------------------------------------------- Total memory size requirement (space wise): Mem Space , Size(KBytes) DDR Cacheable, 22660.45 -------------------------------------------- NOTE: Memory requirement in host emulation can be different from the same on EVM To get the actual TIDL memory requirement make sure to run on EVM with debugTraceLevel = 2 -------------------------------------------- ----TIDLRT_create-----1097---------- ----TIDLRT_create-----1107---------- ----TIDLRT_create-----1125---------- ----TIDLRT_create-----1138---------- TIDL init call from ivision API -------------------------------------------- TIDL Memory size requiement (record wise): MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr 0 , DDR Cacheable , Persistent , 128, 15.25 , 0x7512bd80 1 , DDR Cacheable , Persistent , 128, 0.64 , 0x7512ae00 2 , DDR Cacheable , Scratch , 128, 16.00 , 0x79bf3080 3 , DDR Cacheable , Scratch , 128, 448.00 , 0x79bf7080 4 , DDR Cacheable , Scratch , 128, 2944.00 , 0x79c67080 5 , DDR Cacheable , Persistent , 128, 4743.91 , 0x79068080 6 , DDR Cacheable , Scratch , 128, 7.75 , 0x79f47080 7 , DDR Cacheable , Scratch , 128, 148.25 , 0x79f48f80 8 , DDR Cacheable , Scratch , 128, 4728.12 , 0x79f6e080 9 , DDR Cacheable , Scratch , 128, 1579.00 , 0x7a40c100 10 , DDR Cacheable , Persistent , 128, 447.48 , 0x78ff8080 11 , DDR Cacheable , Scratch , 128, 512.25 , 0x7a596d00 12 , DDR Cacheable , Persistent , 128, 0.12 , 0x7512fb00 13 , DDR Cacheable , Persistent , 128, 7069.64 , 0x78910080 14 , DDR Cacheable , Persistent , 128, 0.03 , 0x7512fc80 -------------------------------------------- Total memory size requirement (space wise): Mem Space , Size(KBytes) DDR Cacheable, 22660.45 -------------------------------------------- NOTE: Memory requirement in host emulation can be different from the same on EVM To get the actual TIDL memory requirement make sure to run on EVM with debugTraceLevel = 2 -------------------------------------------- Algorithm Init failed with error number: -1130 ----tidlMultiInstanceTest-----539---------- Error at line: 545 : in file /home/root/ti-processor-sdk-rtos-j721e-evm-09_01_00_06/c7x-mma-tidl/ti_dl/test/src/pc_linux/../tidl_tb.c, of function : tidlMultiInstanceTest Invalid Error Type! ----tidlMultiInstanceTest-----568---------- ----tidlMultiInstanceTest-----592---------- ----tidlMultiInstanceTest-----594---------- ----tidlMultiInstanceTest-----268---------- ----tidlMultiInstanceTest-----304---------- Processing config file #1 : Couldn't open Parameter Config file . Parser Failed----tidlMultiInstanceTest-----592---------- ----tidlMultiInstanceTest-----594---------- ----tidlMultiInstanceTest-----268---------- ----tidlMultiInstanceTest-----304---------- Processing config file #2 : Couldn't open Parameter Config file . Parser Failed----tidlMultiInstanceTest-----592---------- ----tidlMultiInstanceTest-----594----------