// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for J721S2 SoC Family Main Domain peripherals
 *
 * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
 */
#include <dt-bindings/phy/phy.h>

/ {
	serdes_refclk: serdes-refclk {
		#clock-cells = <0>;
		compatible = "fixed-clock";
	};
};

&cbass_main {
	msmc_ram: sram@70000000 {
		compatible = "mmio-sram";
		reg = <0x0 0x70000000 0x0 0x400000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x0 0x0 0x70000000 0x400000>;

		atf-sram@0 {
			reg = <0x0 0x20000>;
		};

		vpu_sram: vpu-sram@20000 {
			reg = <0x20000 0x1f800>;
		};

		tifs-sram@1f0000 {
			reg = <0x1f0000 0x10000>;
		};

		l3cache-sram@200000 {
			reg = <0x200000 0x200000>;
		};
	};

	scm_conf: scm-conf@104000 {
		compatible = "ti,j721e-system-controller", "syscon", "simple-mfd";
		reg = <0x00 0x00104000 0x00 0x18000>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x00 0x00 0x00104000 0x18000>;

		serdes_ln_ctrl: mux-controller0 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x80 0x3>, <0x84 0x3>, /* SERDES0 lane0/1 select */
					<0x88 0x3>, <0x8c 0x3>; /* SERDES0 lane2/3 select */
		};

		usb_serdes_mux: mux-controller1 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			mux-reg-masks = <0x0 0x8000000>; /* USB0 to SERDES0 lane 1/3 mux */
		};

		edp_serdes_mux: mux-controller2 {
			compatible = "mmio-mux";
			#mux-control-cells = <1>;
			/* EDP0 to SERDES0 lane 0/1 or 2/3 mux */
			mux-reg-masks = <0x310 0x10000000>;
		};

		phy_gmii_sel_cpsw: phy@34 {
			compatible = "ti,am654-phy-gmii-sel";
			reg = <0x34 0x4>;
			#phy-cells = <1>;
		};

		ehrpwm_tbclk: clock-controller@140 {
			compatible = "ti,am654-ehrpwm-tbclk", "syscon";
			reg = <0x140 0x18>;
			#clock-cells = <1>;
		};
	};

	main_ehrpwm0: pwm@3000000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3000000 0x00 0x100>;
		power-domains = <&k3_pds 160 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 0>, <&k3_clks 160 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm1: pwm@3010000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3010000 0x00 0x100>;
		power-domains = <&k3_pds 161 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 1>, <&k3_clks 161 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm2: pwm@3020000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3020000 0x00 0x100>;
		power-domains = <&k3_pds 162 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 2>, <&k3_clks 162 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm3: pwm@3030000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3030000 0x00 0x100>;
		power-domains = <&k3_pds 163 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 3>, <&k3_clks 163 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm4: pwm@3040000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3040000 0x00 0x100>;
		power-domains = <&k3_pds 164 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 4>, <&k3_clks 164 0>;
		clock-names = "tbclk", "fck";
	};

	main_ehrpwm5: pwm@3050000 {
		compatible = "ti,am654-ehrpwm", "ti,am3352-ehrpwm";
		#pwm-cells = <3>;
		reg = <0x00 0x3050000 0x00 0x100>;
		power-domains = <&k3_pds 165 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&ehrpwm_tbclk 5>, <&k3_clks 165 0>;
		clock-names = "tbclk", "fck";
	};

	gic500: interrupt-controller@1800000 {
		compatible = "arm,gic-v3";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0x00 0x01800000 0x00 0x200000>, /* GICD */
		      <0x00 0x01900000 0x00 0x100000>; /* GICR */

		/* vcpumntirq: virtual CPU interface maintenance interrupt */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;

		gic_its: msi-controller@1820000 {
			compatible = "arm,gic-v3-its";
			reg = <0x00 0x01820000 0x00 0x10000>;
			socionext,synquacer-pre-its = <0x1000000 0x400000>;
			msi-controller;
			#msi-cells = <1>;
		};
	};

	main_gpio_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&sms>;
		ti,sci-dev-id = <148>;
		ti,interrupt-ranges = <8 392 56>;
	};

	main_pmx0: pinctrl@11c000 {
		compatible = "pinctrl-single";
		/* Proxy 0 addressing */
		reg = <0x0 0x11c000 0x0 0x120>;
		#pinctrl-cells = <1>;
		pinctrl-single,register-width = <32>;
		pinctrl-single,function-mask = <0xffffffff>;
	};

	main_crypto: crypto@4e00000 {
		compatible = "ti,j721e-sa2ul";
		reg = <0x00 0x4e00000 0x00 0x1200>;
		power-domains = <&k3_pds 297 TI_SCI_PD_SHARED>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x04e00000 0x00 0x04e00000 0x00 0x30000>;

		dmas = <&main_udmap 0xca40>, <&main_udmap 0x4a40>,
				<&main_udmap 0x4a41>;
		dma-names = "tx", "rx1", "rx2";
	};

	main_uart0: serial@2800000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02800000 0x00 0x200>;
		interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 146 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 146 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart1: serial@2810000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02810000 0x00 0x200>;
		interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 350 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 350 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart2: serial@2820000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02820000 0x00 0x200>;
		interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 351 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 351 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart3: serial@2830000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02830000 0x00 0x200>;
		interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 352 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 352 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart4: serial@2840000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02840000 0x00 0x200>;
		interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 353 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 353 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart5: serial@2850000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02850000 0x00 0x200>;
		interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 354 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 354 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart6: serial@2860000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02860000 0x00 0x200>;
		interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 355 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 355 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart7: serial@2870000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02870000 0x00 0x200>;
		interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 356 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 356 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart8: serial@2880000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02880000 0x00 0x200>;
		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 357 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 357 TI_SCI_PD_EXCLUSIVE>;
	};

	main_uart9: serial@2890000 {
		compatible = "ti,j721e-uart", "ti,am654-uart";
		reg = <0x00 0x02890000 0x00 0x200>;
		interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
		current-speed = <115200>;
		clocks = <&k3_clks 358 3>;
		clock-names = "fclk";
		power-domains = <&k3_pds 358 TI_SCI_PD_EXCLUSIVE>;
	};

	gpu: gpu@4e20000000 {
		compatible = "ti,j721s2-pvr", "img,pvr-bxs64";
		reg = <0x4e 0x20000000 0x00 0x80000>;
		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 130 TI_SCI_PD_EXCLUSIVE>,
						<&k3_pds 373 TI_SCI_PD_EXCLUSIVE>;
		power-domain-names = "gpu_0", "gpucore_0";
		clocks = <&k3_clks 130 1>;
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00600000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <145>, <146>, <147>, <148>, <149>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 111 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 111 0>;
		clock-names = "gpio";
	};

	main_gpio2: gpio@610000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00610000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <154>, <155>, <156>, <157>, <158>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 112 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 112 0>;
		clock-names = "gpio";
	};

	main_gpio4: gpio@620000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00620000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <163>, <164>, <165>, <166>, <167>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 113 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 113 0>;
		clock-names = "gpio";
	};

	main_gpio6: gpio@630000 {
		compatible = "ti,j721e-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00630000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <172>, <173>, <174>, <175>, <176>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,ngpio = <66>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 114 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 114 0>;
		clock-names = "gpio";
	};

	main_i2c0: i2c@2000000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02000000 0x00 0x100>;
		interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 214 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c1: i2c@2010000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02010000 0x00 0x100>;
		interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 215 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 215 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c2: i2c@2020000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02020000 0x00 0x100>;
		interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 216 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 216 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c3: i2c@2030000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02030000 0x00 0x100>;
		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 217 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 217 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c4: i2c@2040000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02040000 0x00 0x100>;
		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 218 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 218 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c5: i2c@2050000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02050000 0x00 0x100>;
		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 219 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 219 TI_SCI_PD_EXCLUSIVE>;
	};

	main_i2c6: i2c@2060000 {
		compatible = "ti,j721e-i2c", "ti,omap4-i2c";
		reg = <0x00 0x02060000 0x00 0x100>;
		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 220 1>;
		clock-names = "fck";
		power-domains = <&k3_pds 220 TI_SCI_PD_EXCLUSIVE>;
	};

	vpu: video-codec@4210000 {
		compatible = "cnm,cm521c-vpu";
		reg = <0x00 0x4210000 0x00 0x10000>;
		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&k3_clks 179 2>;
		clock-names = "vcodec";
		power-domains = <&k3_pds 179 TI_SCI_PD_EXCLUSIVE>;
		sram = <&vpu_sram>;
	};

	main_sdhci0: mmc@4f80000 {
		compatible = "ti,j721e-sdhci-8bit";
		reg = <0x00 0x04f80000 0x00 0x1000>,
		      <0x00 0x04f88000 0x00 0x400>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 98 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 98 7>, <&k3_clks 98 1>;
		clock-names =  "clk_ahb", "clk_xin";
		assigned-clocks = <&k3_clks 98 1>;
		assigned-clock-parents = <&k3_clks 98 2>;
		bus-width = <8>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-mmc-hs = <0x0>;
		ti,otap-del-sel-ddr52 = <0x6>;
#if 1	
		ti,otap-del-sel-hs200 = <0x8>;
		ti,otap-del-sel-hs400 = <0x5>;
		ti,itap-del-sel-legacy = <0x10>;
		ti,itap-del-sel-mmc-hs = <0xa>;
#endif
		ti,strobe-sel = <0x77>;
		ti,clkbuf-sel = <0x7>;
		ti,trm-icp = <0x8>;
		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		mmc-hs400-1_8v;
		dma-coherent;
	};

	main_sdhci1: mmc@4fb0000 {
		compatible = "ti,j721e-sdhci-4bit";
		reg = <0x00 0x04fb0000 0x00 0x1000>,
		      <0x00 0x04fb8000 0x00 0x400>;
		interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
		power-domains = <&k3_pds 99 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 99 8>, <&k3_clks 99 1>;
		clock-names =  "clk_ahb", "clk_xin";
		assigned-clocks = <&k3_clks 99 1>;
		assigned-clock-parents = <&k3_clks 99 2>;
		bus-width = <4>;
		ti,otap-del-sel-legacy = <0x0>;
		ti,otap-del-sel-sd-hs = <0x0>;
		ti,otap-del-sel-sdr12 = <0xf>;
		ti,otap-del-sel-sdr25 = <0xf>;
		ti,otap-del-sel-sdr50 = <0xc>;
		ti,otap-del-sel-sdr104 = <0x5>;
		ti,otap-del-sel-ddr50 = <0xc>;
		ti,itap-del-sel-legacy = <0x0>;
		ti,itap-del-sel-sd-hs = <0x0>;
		ti,itap-del-sel-sdr12 = <0x0>;
		ti,itap-del-sel-sdr25 = <0x0>;
		ti,clkbuf-sel = <0x7>;
		ti,trm-icp = <0x8>;
		dma-coherent;
		/* Masking support for SDR104 capability */
		sdhci-caps-mask = <0x00000003 0x00000000>;
	};

	main_navss: bus@30000000 {
		compatible = "simple-mfd";
		#address-cells = <2>;
		#size-cells = <2>;
		ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
		ti,sci-dev-id = <224>;
		dma-coherent;
		dma-ranges;

		main_navss_intr: interrupt-controller@310e0000 {
			compatible = "ti,sci-intr";
			reg = <0x00 0x310e0000 0x00 0x4000>;
			ti,intr-trigger-type = <4>;
			interrupt-controller;
			interrupt-parent = <&gic500>;
			#interrupt-cells = <1>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <227>;
			ti,interrupt-ranges = <0 64 64>,
					      <64 448 64>,
					      <128 672 64>;
		};

		main_udmass_inta: msi-controller@33d00000 {
			compatible = "ti,sci-inta";
			reg = <0x00 0x33d00000 0x00 0x100000>;
			interrupt-controller;
			#interrupt-cells = <0>;
			interrupt-parent = <&main_navss_intr>;
			msi-controller;
			ti,sci = <&sms>;
			ti,sci-dev-id = <265>;
			ti,interrupt-ranges = <0 0 256>;
			ti,unmapped-event-sources = <&main_bcdma_csi>;
		};

		secure_proxy_main: mailbox@32c00000 {
			compatible = "ti,am654-secure-proxy";
			#mbox-cells = <1>;
			reg-names = "target_data", "rt", "scfg";
			reg = <0x00 0x32c00000 0x00 0x100000>,
			      <0x00 0x32400000 0x00 0x100000>,
			      <0x00 0x32800000 0x00 0x100000>;
			interrupt-names = "rx_011";
			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		};

		hwspinlock: spinlock@30e00000 {
			compatible = "ti,am654-hwspinlock";
			reg = <0x00 0x30e00000 0x00 0x1000>;
			#hwlock-cells = <1>;
		};

		mailbox0_cluster0: mailbox@31f80000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f80000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster1: mailbox@31f81000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f81000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster2: mailbox@31f82000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f82000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster3: mailbox@31f83000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f83000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster4: mailbox@31f84000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f84000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster5: mailbox@31f85000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f85000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster6: mailbox@31f86000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f86000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster7: mailbox@31f87000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f87000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster8: mailbox@31f88000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f88000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster9: mailbox@31f89000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f89000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster10: mailbox@31f8a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox0_cluster11: mailbox@31f8b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f8b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster0: mailbox@31f90000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f90000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster1: mailbox@31f91000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f91000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster2: mailbox@31f92000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f92000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster3: mailbox@31f93000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f93000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster4: mailbox@31f94000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f94000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster5: mailbox@31f95000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f95000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster6: mailbox@31f96000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f96000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster7: mailbox@31f97000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f97000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster8: mailbox@31f98000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f98000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster9: mailbox@31f99000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f99000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster10: mailbox@31f9a000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f9a000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		mailbox1_cluster11: mailbox@31f9b000 {
			compatible = "ti,am654-mailbox";
			reg = <0x00 0x31f9b000 0x00 0x200>;
			#mbox-cells = <1>;
			ti,mbox-num-users = <4>;
			ti,mbox-num-fifos = <16>;
			interrupt-parent = <&main_navss_intr>;
		};

		main_ringacc: ringacc@3c000000 {
			compatible = "ti,am654-navss-ringacc";
			reg = <0x0 0x3c000000 0x0 0x400000>,
			      <0x0 0x38000000 0x0 0x400000>,
			      <0x0 0x31120000 0x0 0x100>,
			      <0x0 0x33000000 0x0 0x40000>;
			reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target";
			ti,num-rings = <1024>;
			ti,sci-rm-range-gp-rings = <0x1>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <259>;
			msi-parent = <&main_udmass_inta>;
		};

		main_udmap: dma-controller@31150000 {
			compatible = "ti,j721e-navss-main-udmap";
			reg = <0x0 0x31150000 0x0 0x100>,
			      <0x0 0x34000000 0x0 0x80000>,
			      <0x0 0x35000000 0x0 0x200000>;
			reg-names = "gcfg", "rchanrt", "tchanrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <1>;

			ti,sci = <&sms>;
			ti,sci-dev-id = <263>;
			ti,ringacc = <&main_ringacc>;

			ti,sci-rm-range-tchan = <0x0d>, /* TX_CHAN */
						<0x0f>, /* TX_HCHAN */
						<0x10>; /* TX_UHCHAN */
			ti,sci-rm-range-rchan = <0x0a>, /* RX_CHAN */
						<0x0b>, /* RX_HCHAN */
						<0x0c>; /* RX_UHCHAN */
			ti,sci-rm-range-rflow = <0x00>; /* GP RFLOW */
		};

		main_bcdma_csi: dma-controller@311a0000 {
			compatible = "ti,j721s2-dmss-bcdma-csi";
			reg = <0x00 0x311a0000 0x00 0x100>,
				<0x00 0x35d00000 0x00 0x20000>,
				<0x00 0x35c00000 0x00 0x10000>,
				<0x00 0x35e00000 0x00 0x80000>;
			reg-names = "gcfg", "rchanrt", "tchanrt", "ringrt";
			msi-parent = <&main_udmass_inta>;
			#dma-cells = <3>;
			ti,sci = <&sms>;
			ti,sci-dev-id = <225>;
			ti,sci-rm-range-rchan = <0x21>;
			ti,sci-rm-range-tchan = <0x22>;
		};

		cpts@310d0000 {
			compatible = "ti,j721e-cpts";
			reg = <0x0 0x310d0000 0x0 0x400>;
			reg-names = "cpts";
			clocks = <&k3_clks 226 5>;
			clock-names = "cpts";
			interrupts-extended = <&main_navss_intr 391>;
			interrupt-names = "cpts";
			ti,cpts-periodic-outputs = <6>;
			ti,cpts-ext-ts-inputs = <8>;
		};
	};

	main_cpsw: ethernet@c200000 {
		compatible = "ti,j721e-cpsw-nuss";
		#address-cells = <2>;
		#size-cells = <2>;
		reg = <0x0 0xc200000 0x0 0x200000>;
		reg-names = "cpsw_nuss";
		ranges = <0x0 0x0 0x0 0xc200000 0x0 0x200000>;
		dma-coherent;
		clocks = <&k3_clks 28 28>;
		clock-names = "fck";
		power-domains = <&k3_pds 28 TI_SCI_PD_EXCLUSIVE>;

		dmas = <&main_udmap 0xc640>,
		       <&main_udmap 0xc641>,
		       <&main_udmap 0xc642>,
		       <&main_udmap 0xc643>,
		       <&main_udmap 0xc644>,
		       <&main_udmap 0xc645>,
		       <&main_udmap 0xc646>,
		       <&main_udmap 0xc647>,
		       <&main_udmap 0x4640>;
		dma-names = "tx0", "tx1", "tx2", "tx3",
			    "tx4", "tx5", "tx6", "tx7",
			    "rx";

		ethernet-ports {
			#address-cells = <1>;
			#size-cells = <0>;

			main_cpsw_port1: port@1 {
				reg = <1>;
				ti,mac-only;
				label = "port1";
				phys = <&phy_gmii_sel_cpsw 1>;
			};
		};

		main_cpsw_mdio: mdio@f00 {
			compatible = "ti,cpsw-mdio","ti,davinci_mdio";
			reg = <0x0 0xf00 0x0 0x100>;
			#address-cells = <1>;
			#size-cells = <0>;
			clocks = <&k3_clks 28 28>;
			clock-names = "fck";
			bus_freq = <1000000>;
		};

		cpts@3d000 {
			compatible = "ti,am65-cpts";
			reg = <0x0 0x3d000 0x0 0x400>;
			clocks = <&k3_clks 28 3>;
			clock-names = "cpts";
			interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "cpts";
			ti,cpts-ext-ts-inputs = <4>;
			ti,cpts-periodic-outputs = <2>;
		};
	};

	usbss0: cdns-usb@4104000 {
		compatible = "ti,j721e-usb";
		reg = <0x00 0x04104000 0x00 0x100>;
		clocks = <&k3_clks 360 16>, <&k3_clks 360 15>;
		clock-names = "ref", "lpm";
		assigned-clocks = <&k3_clks 360 16>; /* USB2_REFCLK */
		assigned-clock-parents = <&k3_clks 360 17>;
		power-domains = <&k3_pds 360 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;
		dma-coherent;

		usb0: usb@6000000 {
			compatible = "cdns,usb3";
			reg = <0x00 0x06000000 0x00 0x10000>,
			      <0x00 0x06010000 0x00 0x10000>,
			      <0x00 0x06020000 0x00 0x10000>;
			reg-names = "otg", "xhci", "dev";
			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
			 interrupt-names = "host", "peripheral", "otg";
			 maximum-speed = "super-speed";
			 dr_mode = "otg";
		};
	};

	serdes_wiz0: wiz@5060000 {
		compatible = "ti,j721e-wiz-10g";
		#address-cells = <1>;
		#size-cells = <1>;
		power-domains = <&k3_pds 365 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 365 0>, <&k3_clks 365 3>, <&serdes_refclk>;
		clock-names = "fck", "core_ref_clk", "ext_ref_clk";
		num-lanes = <4>;
		#reset-cells = <1>;
		ranges = <0x5060000 0x0 0x5060000 0x10000>,
			 <0xa030a00 0x0 0xa030a00 0x40>; /* DPTX PHY */

		assigned-clocks = <&k3_clks 365 3>;
		assigned-clock-parents = <&k3_clks 365 7>;

		wiz0_pll0_refclk: pll0-refclk {
			clocks = <&k3_clks 365 3>, <&serdes_refclk>;
			clock-output-names = "wiz0_pll0_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll0_refclk>;
			assigned-clock-parents = <&k3_clks 365 3>;
		};

		wiz0_pll1_refclk: pll1-refclk {
			clocks = <&k3_clks 365 3>, <&serdes_refclk>;
			clock-output-names = "wiz0_pll1_refclk";
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_pll1_refclk>;
			assigned-clock-parents = <&k3_clks 365 3>;
		};

		wiz0_refclk_dig: refclk-dig {
			clocks = <&k3_clks 365 3>, <&serdes_refclk>;
			clock-output-names = "wiz0_refclk_dig";
			#clock-cells = <0>;
			assigned-clocks = <&wiz0_refclk_dig>;
			assigned-clock-parents = <&k3_clks 365 3>;
		};

		wiz0_cmn_refclk_dig_div: cmn-refclk-dig-div {
			clocks = <&wiz0_refclk_dig>;
			#clock-cells = <0>;
		};

		serdes0: serdes@5060000 {
			/*
			 * Note: we also map DPTX PHY registers as the Torrent
			 * needs to manage those.
			 */
			compatible = "ti,j721e-serdes-10g";
			reg = <0x05060000 0x00010000>,
			      <0xa030a00 0x40>; /* DPTX PHY */
			reg-names = "torrent_phy", "dptx_phy";
			resets = <&serdes_wiz0 0>;
			reset-names = "torrent_reset";
			clocks = <&wiz0_pll0_refclk>;
			clock-names = "refclk";
			#address-cells = <1>;
			#size-cells = <0>;

			torrent_phy_dp: phy@2 {
				reg = <2>;
				resets = <&serdes_wiz0 3>;
				cdns,phy-type = <PHY_TYPE_DP>;
				cdns,num-lanes = <2>;
				cdns,max-bit-rate = <5400>;
				#phy-cells = <0>;
				status = "disabled";
			};
		};
	};

	pcie1_rc: pcie@2910000 {
		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x00001000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		device_type = "pci";
		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
		max-link-speed = <3>;
		num-lanes = <4>;
		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 276 41>;
		clock-names = "fck";
		#address-cells = <3>;
		#size-cells = <2>;
		bus-range = <0x0 0xff>;
		vendor-id = <0x104c>;
		device-id = <0xb013>;
		msi-map = <0x0 &gic_its 0x0 0x10000>;
		dma-coherent;
		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 7>;
		interrupt-map = <0 0 0 1 &pcie1_intc 0>, /* INT A */
				<0 0 0 2 &pcie1_intc 0>, /* INT B */
				<0 0 0 3 &pcie1_intc 0>, /* INT C */
				<0 0 0 4 &pcie1_intc 0>; /* INT D */

		pcie1_intc: interrupt-controller {
			interrupt-controller;
			#interrupt-cells = <1>;
			interrupt-parent = <&gic500>;
			interrupts = <GIC_SPI 324 IRQ_TYPE_EDGE_RISING>;
		};
	};

	pcie1_ep: pcie-ep@2910000 {
		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
		reg = <0x00 0x02910000 0x00 0x1000>,
		      <0x00 0x02917000 0x00 0x400>,
		      <0x00 0x0d800000 0x00 0x00800000>,
		      <0x00 0x18000000 0x00 0x08000000>;
		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
		interrupt-names = "link_state";
		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
		max-link-speed = <3>;
		num-lanes = <4>;
		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 276 41>;
		clock-names = "fck";
		max-functions = /bits/ 8 <6>;
		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
		dma-coherent;
	};

	main_r5fss0: r5fss@5c00000 {
		compatible = "ti,j721s2-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5c00000 0x00 0x5c00000 0x20000>,
			 <0x5d00000 0x00 0x5d00000 0x20000>;
		power-domains = <&k3_pds 277 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss0_core0: r5f@5c00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5c00000 0x00010000>,
			      <0x5c10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <279>;
			ti,sci-proc-ids = <0x06 0xff>;
			resets = <&k3_reset 279 1>;
			firmware-name = "j721s2-main-r5f0_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss0_core1: r5f@5d00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5d00000 0x00010000>,
			      <0x5d10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <280>;
			ti,sci-proc-ids = <0x07 0xff>;
			resets = <&k3_reset 280 1>;
			firmware-name = "j721s2-main-r5f0_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	main_r5fss1: r5fss@5e00000 {
		compatible = "ti,j721s2-r5fss";
		ti,cluster-mode = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges = <0x5e00000 0x00 0x5e00000 0x20000>,
			 <0x5f00000 0x00 0x5f00000 0x20000>;
		power-domains = <&k3_pds 278 TI_SCI_PD_EXCLUSIVE>;

		main_r5fss1_core0: r5f@5e00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5e00000 0x00010000>,
			      <0x5e10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <281>;
			ti,sci-proc-ids = <0x08 0xff>;
			resets = <&k3_reset 281 1>;
			firmware-name = "j721s2-main-r5f1_0-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};

		main_r5fss1_core1: r5f@5f00000 {
			compatible = "ti,j721s2-r5f";
			reg = <0x5f00000 0x00010000>,
			      <0x5f10000 0x00010000>;
			reg-names = "atcm", "btcm";
			ti,sci = <&sms>;
			ti,sci-dev-id = <282>;
			ti,sci-proc-ids = <0x09 0xff>;
			resets = <&k3_reset 282 1>;
			firmware-name = "j721s2-main-r5f1_1-fw";
			ti,atcm-enable = <1>;
			ti,btcm-enable = <1>;
			ti,loczrama = <1>;
		};
	};

	c71_0: dsp@64800000 {
		compatible = "ti,j721s2-c71-dsp";
		reg = <0x00 0x64800000 0x00 0x00080000>,
		      <0x00 0x64e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&sms>;
		ti,sci-dev-id = <8>;
		ti,sci-proc-ids = <0x30 0xff>;
		resets = <&k3_reset 8 1>;
		firmware-name = "j721s2-c71_0-fw";
	};

	c71_1: dsp@65800000 {
		compatible = "ti,j721s2-c71-dsp";
		reg = <0x00 0x65800000 0x00 0x00080000>,
		      <0x00 0x65e00000 0x00 0x0000c000>;
		reg-names = "l2sram", "l1dram";
		ti,sci = <&sms>;
		ti,sci-dev-id = <11>;
		ti,sci-proc-ids = <0x31 0xff>;
		resets = <&k3_reset 11 1>;
		firmware-name = "j721s2-c71_1-fw";
	};

	main_mcan0: can@2701000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02701000 0x00 0x200>,
		      <0x00 0x02708000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 182 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 182 0>, <&k3_clks 182 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan1: can@2711000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02711000 0x00 0x200>,
		      <0x00 0x02718000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 183 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 183 0>, <&k3_clks 183 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan2: can@2721000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02721000 0x00 0x200>,
		      <0x00 0x02728000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 184 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 184 0>, <&k3_clks 184 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan3: can@2731000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02731000 0x00 0x200>,
		      <0x00 0x02738000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 185 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 185 0>, <&k3_clks 185 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan4: can@2741000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02741000 0x00 0x200>,
		      <0x00 0x02748000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 186 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 186 0>, <&k3_clks 186 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan5: can@2751000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02751000 0x00 0x200>,
		      <0x00 0x02758000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 187 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 187 0>, <&k3_clks 187 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan6: can@2761000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02761000 0x00 0x200>,
		      <0x00 0x02768000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 188 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 188 0>, <&k3_clks 188 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan7: can@2771000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02771000 0x00 0x200>,
		      <0x00 0x02778000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 189 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 189 0>, <&k3_clks 189 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan8: can@2781000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02781000 0x00 0x200>,
		      <0x00 0x02788000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 190 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 190 0>, <&k3_clks 190 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan9: can@2791000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02791000 0x00 0x200>,
		      <0x00 0x02798000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 191 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 191 0>, <&k3_clks 191 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 579 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 580 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan10: can@27a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027a1000 0x00 0x200>,
		      <0x00 0x027a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 192 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 192 0>, <&k3_clks 192 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan11: can@27b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027b1000 0x00 0x200>,
		      <0x00 0x027b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 193 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 193 0>, <&k3_clks 193 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan12: can@27c1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027c1000 0x00 0x200>,
		      <0x00 0x027c8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 194 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 194 0>, <&k3_clks 194 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan13: can@27d1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x027d1000 0x00 0x200>,
		      <0x00 0x027d8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 195 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 195 0>, <&k3_clks 195 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan14: can@2681000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02681000 0x00 0x200>,
		      <0x00 0x02688000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 197 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 197 0>, <&k3_clks 197 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan15: can@2691000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x02691000 0x00 0x200>,
		      <0x00 0x02698000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 199 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 199 0>, <&k3_clks 199 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan16: can@26a1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x026a1000 0x00 0x200>,
		      <0x00 0x026a8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 201 0>, <&k3_clks 201 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_mcan17: can@26b1000 {
		compatible = "bosch,m_can";
		reg = <0x00 0x026b1000 0x00 0x200>,
		      <0x00 0x026b8000 0x00 0x8000>;
		reg-names = "m_can", "message_ram";
		power-domains = <&k3_pds 206 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 206 0>, <&k3_clks 206 1>;
		clock-names = "hclk", "cclk";
		interrupts = <GIC_SPI 787 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 788 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "int0", "int1";
		bosch,mram-cfg = <0x0 128 64 64 64 64 32 32>;
	};

	main_spi0: spi@2100000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02100000 0x00 0x400>;
		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 339 1>;
		power-domains = <&k3_pds 339 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi1: spi@2110000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02110000 0x00 0x400>;
		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 340 1>;
		power-domains = <&k3_pds 340 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi2: spi@2120000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02120000 0x00 0x400>;
		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 341 1>;
		power-domains = <&k3_pds 341 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi3: spi@2130000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02130000 0x00 0x400>;
		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 342 1>;
		power-domains = <&k3_pds 342 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi4: spi@2140000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02140000 0x00 0x400>;
		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 343 1>;
		power-domains = <&k3_pds 343 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi5: spi@2150000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02150000 0x00 0x400>;
		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 344 1>;
		power-domains = <&k3_pds 344 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi6: spi@2160000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02160000 0x00 0x400>;
		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 345 1>;
		power-domains = <&k3_pds 345 TI_SCI_PD_EXCLUSIVE>;
	};

	main_spi7: spi@2170000 {
		compatible = "ti,am654-mcspi","ti,omap4-mcspi";
		reg = <0x00 0x02170000 0x00 0x400>;
		interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&k3_clks 346 1>;
		power-domains = <&k3_pds 346 TI_SCI_PD_EXCLUSIVE>;
	};

	mhdp: dp-bridge@a000000 {
		compatible = "ti,j721e-mhdp8546";
		/*
		 * Note: we do not map DPTX PHY area, as that is handled by
		 * the PHY driver.
		 */
		reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */
		      <0x0 0x4f40000 0x0 0x20>;    /* DSS_EDP0_INTG_CFG_VP */
		reg-names = "mhdptx", "j721e-intg";

		clocks = <&k3_clks 156 19>;

		phys = <&torrent_phy_dp>;
		phy-names = "dpphy";

		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>;

		power-domains = <&k3_pds 156 TI_SCI_PD_EXCLUSIVE>;

		dp0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
		};
	};

	dphy0: phy@4480000 {
		compatible = "ti,j721e-dphy";
		reg = <0x0 0x04480000 0x0 0x1000>;
		clocks = <&k3_clks 363 8>, <&k3_clks 363 14>;
		clock-names = "psm", "pll_ref";
		#phy-cells = <0>;
		power-domains = <&k3_pds 363 TI_SCI_PD_EXCLUSIVE>;
		assigned-clocks = <&k3_clks 363 14>;
		assigned-clock-parents = <&k3_clks 363 15>;
		assigned-clock-rates = <19200000>;
	};

	dsi0: dsi@4800000 {
		compatible = "ti,j721e-dsi";
		reg = <0x0 0x04800000 0x0 0x100000>, <0x0 0x04710000 0x0 0x100>;
		clocks = <&k3_clks 154 4>, <&k3_clks 154 1>;
		clock-names = "dsi_p_clk", "dsi_sys_clk";
		power-domains = <&k3_pds 154 TI_SCI_PD_EXCLUSIVE>;
		interrupt-parent = <&gic500>;
		interrupts = <GIC_SPI 600 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&dphy0>;
		phy-names = "dphy";

		dsi0_ports: ports {
			#address-cells = <1>;
			#size-cells = <0>;
			port@0 {
				reg = <0>;
			};
			port@1 {
				reg = <1>;
			};
		};
	};

	dss: dss@4a00000 {
		compatible = "ti,j721e-dss";
		reg =
			<0x00 0x04a00000 0x00 0x10000>, /* common_m */
			<0x00 0x04a10000 0x00 0x10000>, /* common_s0*/
			<0x00 0x04b00000 0x00 0x10000>, /* common_s1*/
			<0x00 0x04b10000 0x00 0x10000>, /* common_s2*/

			<0x00 0x04a20000 0x00 0x10000>, /* vidl1 */
			<0x00 0x04a30000 0x00 0x10000>, /* vidl2 */
			<0x00 0x04a50000 0x00 0x10000>, /* vid1 */
			<0x00 0x04a60000 0x00 0x10000>, /* vid2 */

			<0x00 0x04a70000 0x00 0x10000>, /* ovr1 */
			<0x00 0x04a90000 0x00 0x10000>, /* ovr2 */
			<0x00 0x04ab0000 0x00 0x10000>, /* ovr3 */
			<0x00 0x04ad0000 0x00 0x10000>, /* ovr4 */

			<0x00 0x04a80000 0x00 0x10000>, /* vp1 */
			<0x00 0x04aa0000 0x00 0x10000>, /* vp2 */
			<0x00 0x04ac0000 0x00 0x10000>, /* vp3 */
			<0x00 0x04ae0000 0x00 0x10000>, /* vp4 */
			<0x00 0x04af0000 0x00 0x10000>; /* wb */

		reg-names = "common_m", "common_s0",
			"common_s1", "common_s2",
			"vidl1", "vidl2","vid1","vid2",
			"ovr1", "ovr2", "ovr3", "ovr4",
			"vp1", "vp2", "vp3", "vp4",
			"wb";

		clocks =	<&k3_clks 158 0>,
				<&k3_clks 158 2>,
				<&k3_clks 158 5>,
				<&k3_clks 158 14>,
				<&k3_clks 158 18>;
		clock-names = "fck", "vp1", "vp2", "vp3", "vp4";

		power-domains = <&k3_pds 158 TI_SCI_PD_EXCLUSIVE>;

		interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "common_m",
				  "common_s0",
				  "common_s1",
				  "common_s2";

		dss_ports: ports {
		};
	};

	ti_csi2rx0: ticsi2rx@4500000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_bcdma_csi 0 0x4940 0>, <&main_bcdma_csi 0 0x4941 0>,
		<&main_bcdma_csi 0 0x4942 0>, <&main_bcdma_csi 0 0x4943 0>,
		<&main_bcdma_csi 0 0x4944 0>, <&main_bcdma_csi 0 0x4945 0>,
		<&main_bcdma_csi 0 0x4946 0>, <&main_bcdma_csi 0 0x4947 0>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
		reg = <0x00 0x04500000 0x00 0x1000>;
		power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx0: csi-bridge@4504000 {
			compatible = "cdns,csi2rx";
			reg = <0x00 0x04504000 0x00 0x1000>;
			clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>,
				<&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy_rx0>;
			phy-names = "dphy";
			power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi0_port0: port@0 {
					reg = <0>;
				};

				csi0_port1: port@1 {
					reg = <1>;
				};

				csi0_port2: port@2 {
					reg = <2>;
				};

				csi0_port3: port@3 {
					reg = <3>;
				};

				csi0_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	ti_csi2rx1: ticsi2rx@4510000 {
		compatible = "ti,j721e-csi2rx";
		dmas = <&main_bcdma_csi 0 0x4960 0>, <&main_bcdma_csi 0 0x4961 0>,
		<&main_bcdma_csi 0 0x4962 0>, <&main_bcdma_csi 0 0x4963 0>,
		<&main_bcdma_csi 0 0x4964 0>, <&main_bcdma_csi 0 0x4965 0>,
		<&main_bcdma_csi 0 0x4966 0>, <&main_bcdma_csi 0 0x4967 0>;
		dma-names = "rx0", "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7";
		reg = <0x00 0x04510000 0x00 0x1000>;
		power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		cdns_csi2rx1: csi-bridge@4514000 {
			compatible = "cdns,csi2rx";
			reg = <0x00 0x04514000 0x00 0x1000>;
			clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>,
				<&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>;
			clock-names = "sys_clk", "p_clk", "pixel_if0_clk",
				"pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk";
			phys = <&dphy_rx1>;
			phy-names = "dphy";
			power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>;

			ports {
				#address-cells = <1>;
				#size-cells = <0>;

				csi1_port0: port@0 {
					reg = <0>;
				};

				csi1_port1: port@1 {
					reg = <1>;
				};

				csi1_port2: port@2 {
					reg = <2>;
				};

				csi1_port3: port@3 {
					reg = <3>;
				};

				csi1_port4: port@4 {
					reg = <4>;
				};
			};
		};
	};

	dphy_rx0: phy@4580000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x00 0x04580000 0x00 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>;
	};

	dphy_rx1: phy@4590000 {
		compatible = "ti,j721e-dphy", "cdns,dphy";
		reg = <0x00 0x04590000 0x00 0x1100>;
		#phy-cells = <0>;
		power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>;
	};
};