int srio_Dio_Port_Init(SRIO_DIO_INIT_OPT_T* pInitOptions, SRIO_DIO_BOOL_T enableLoopback, SRIO_DIO_BOOL_T enablePeerReset)
{

    /* This Initialization code is for interface with RIOCLK = 156.25Mhz */
    Uint32  srio_4P_1X_Mode=0, rdata=0, wdata=0, mdata=0, mask=0, i=0;

    /* Set the Four port flag {enhanced mode} if configured.*/
    if (pInitOptions->portWidth == SRIO_ACCESS_4P_1X)
    {
        srio_4P_1X_Mode = 1;
    }

    /*------------------------------------------------------------------------------------**
    **     Peripheral Global Enable Register (GBL_EN) & Block n Enable Register (BLKn_EN) **
    **------------------------------------------------------------------------------------*/
    SRIO_REGS->GBL_EN 					= CSL_SRIO_GBL_EN_EN_ENABLE;
    SRIO_REGS->BLK_ENABLE[0].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE;	//MMR_EN
    SRIO_REGS->BLK_ENABLE[5].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;   //PORT0_EN
    SRIO_REGS->BLK_ENABLE[1].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;	//LSU_EN
    SRIO_REGS->BLK_ENABLE[2].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;	//MAU_EN
    SRIO_REGS->BLK_ENABLE[3].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;	//TXU_EN
    SRIO_REGS->BLK_ENABLE[4].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;	//RXU_EN
    SRIO_REGS->BLK_ENABLE[6].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;   //PORT1_EN
    SRIO_REGS->BLK_ENABLE[7].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;   //PORT2_EN
    SRIO_REGS->BLK_ENABLE[8].BLK_EN 	= CSL_SRIO_BLK_EN_EN_DISABLE;   //PORT3_EN

    SRIO_REGS->BLK_ENABLE[5].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;   //PORT0_EN
    SRIO_REGS->BLK_ENABLE[1].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;	//LSU_EN
    SRIO_REGS->BLK_ENABLE[2].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;	//MAU_EN
    SRIO_REGS->BLK_ENABLE[3].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;	//TXU_EN
    SRIO_REGS->BLK_ENABLE[4].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;	//RXU_EN
    SRIO_REGS->BLK_ENABLE[6].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;   //PORT1_EN
    SRIO_REGS->BLK_ENABLE[7].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;   //PORT2_EN
    SRIO_REGS->BLK_ENABLE[8].BLK_EN 	= CSL_SRIO_BLK_EN_EN_ENABLE ;   //PORT3_EN


    /*--------------------------------------------------------**
    ** 	 Peripheral Settings Control Register (PER_SET_CNTL). **
    **--------------------------------------------------------*/

    wdata = CSL_FMKT(SRIO_PER_SET_CNTL_ENPLL1,ENABLE)       | \
        CSL_FMKT(SRIO_PER_SET_CNTL_PRESCALER_SELECT,5)  | \
        CSL_FMKT(SRIO_PER_SET_CNTL_BOOT_COMPLETE,WRITE_DISABLE);

    if (srio_4P_1X_Mode)
    {
        wdata |= CSL_FMKT(SRIO_PER_SET_CNTL_ENPLL2,ENABLE)   | \
            CSL_FMKT(SRIO_PER_SET_CNTL_ENPLL3,ENABLE)   | \
            CSL_FMKT(SRIO_PER_SET_CNTL_1X_MODE,ENABLE)  | \
            CSL_FMKT(SRIO_PER_SET_CNTL_ENPLL4,ENABLE);
    }

    if (enableLoopback)
    {
        wdata |= CSL_FMKT(SRIO_PER_SET_CNTL_LOOPBACK,LOOPBACK);
    }

    mask  = CSL_MMK(SRIO_PER_SET_CNTL_ENPLL1)           | \
        CSL_MMK(SRIO_PER_SET_CNTL_PRESCALER_SELECT) | \
        CSL_MMK(SRIO_PER_SET_CNTL_BOOT_COMPLETE)    | \
        CSL_MMK(SRIO_PER_SET_CNTL_ENPLL2)           | \
        CSL_MMK(SRIO_PER_SET_CNTL_ENPLL3)           | \
        CSL_MMK(SRIO_PER_SET_CNTL_ENPLL4)           | \
        CSL_MMK(SRIO_PER_SET_CNTL_1X_MODE)          | \
        CSL_MMK(SRIO_PER_SET_CNTL_LOOPBACK);


    rdata = SRIO_REGS->PER_SET_CNTL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->PER_SET_CNTL	= mdata ;  

#ifndef DSK_64XX
    /* Serdes configuration for the required port speed*/
    IDT_AMC_Configure_Serdes_Control(0,pInitOptions->port0Speed);
    if (srio_4P_1X_Mode)
    {
        IDT_AMC_Configure_Serdes_Control(1,pInitOptions->port1Speed);
        IDT_AMC_Configure_Serdes_Control(2,pInitOptions->port2Speed);
        IDT_AMC_Configure_Serdes_Control(3,pInitOptions->port3Speed);
    }
    else
    {
        IDT_AMC_Configure_Serdes_Control(1,pInitOptions->port0Speed);
        IDT_AMC_Configure_Serdes_Control(2,pInitOptions->port0Speed);
        IDT_AMC_Configure_Serdes_Control(3,pInitOptions->port0Speed);        
    }
#else
    /* Serdes configuration for the required port speed*/
    TI_DSK_Configure_Serdes_Control(0,pInitOptions->port0Speed);
    if (srio_4P_1X_Mode)
    {
        TI_DSK_Configure_Serdes_Control(1,pInitOptions->port1Speed);
        TI_DSK_Configure_Serdes_Control(2,pInitOptions->port2Speed);
        TI_DSK_Configure_Serdes_Control(3,pInitOptions->port3Speed);
    }
    else
    {
        TI_DSK_Configure_Serdes_Control(1,pInitOptions->port0Speed);
        TI_DSK_Configure_Serdes_Control(2,pInitOptions->port0Speed);
        TI_DSK_Configure_Serdes_Control(3,pInitOptions->port0Speed);
    }
#endif

    /*------------------------------------------------**
    **     RapidIO DEVICEID1 Register (DEVICEID_REG1) **
    **------------------------------------------------*/

    wdata = CSL_FMK(SRIO_DEVICEID_REG1_8BNODEID,pInitOptions->smallDevId)   | \
        CSL_FMK(SRIO_DEVICEID_REG1_16BNODEID,pInitOptions->largeDevId);

        mask  = CSL_MMK(SRIO_DEVICEID_REG1_8BNODEID)    | \
        CSL_MMK(SRIO_DEVICEID_REG1_16BNODEID);

        rdata = SRIO_REGS->DEVICEID_REG1;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->DEVICEID_REG1 = mdata ; 

    /*------------------------------------------------**
    **     RapidIO DEVICEID2 Register (DEVICEID_REG2) **
    **------------------------------------------------*/

        wdata = CSL_FMK(SRIO_DEVICEID_REG2_8BNODEID,pInitOptions->smallMcastDevId)   | \
        CSL_FMK(SRIO_DEVICEID_REG2_16BNODEID,pInitOptions->largeMcastDevId);

        mask  = CSL_MMK(SRIO_DEVICEID_REG2_8BNODEID)    | \
        CSL_MMK(SRIO_DEVICEID_REG2_16BNODEID);

        rdata = SRIO_REGS->DEVICEID_REG2;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->DEVICEID_REG2 = mdata ; 

    /*-------------------------------------------------------------------**
    **                                                                   **
    **     Setup the interrupts for SRIO.                                **
    **                                                                   **
    **     Note : Interrupt mapping for SRIO peripheral in 6455/6482 DSP **
    **     INT_DST0 -> RIO_INT0 -> EVENT 20                              **
    **     INT_DST1 -> RIO_INT1 -> EVENT 21                              **
    **     INT_DST4 -> RIO_INT4 -> EVENT 22                              **
    **                                                                   **
    **-------------------------------------------------------------------*/

    /*----------------------------------------------**
    **     LSU Clear Interrupt Register (LSU _ICCR) **
    **----------------------------------------------*/
    SRIO_REGS->LSU_ICCR		    = 0xFFFFFFFF ; 

    /*------------------------------------------------------------------**
    **     LSU Module Interrupt Condition Routing Register  (LSU_ICRRx) **
    **------------------------------------------------------------------*/

    /*Route all LSU interrupts to intdst0 [or EVENT 20 refer table in section Interrupt Sources 
    and Interrupt Controller of 6455/6482 datasheet]*/
    SRIO_REGS->LSU_ICRR[0]		= 0x00000000 ;  
    SRIO_REGS->LSU_ICRR[1]		= 0x00000000 ;  
    SRIO_REGS->LSU_ICRR[2]		= 0x00000000 ;  
    SRIO_REGS->LSU_ICRR[3]		= 0x00000000 ;  

    /*---------------------------------------------------------**
    **     DOORBELLn Interrupt Clear Register (DOORBELLn_ICCR) **
    **---------------------------------------------------------*/
    SRIO_REGS->DOORBELL_INTR[0].DOORBELL_ICCR 	= 0xFFFFFFFF;       
    SRIO_REGS->DOORBELL_INTR[1].DOORBELL_ICCR 	= 0xFFFFFFFF;     
    SRIO_REGS->DOORBELL_INTR[2].DOORBELL_ICCR 	= 0xFFFFFFFF;     
    SRIO_REGS->DOORBELL_INTR[3].DOORBELL_ICCR 	= 0xFFFFFFFF;     

    /*--------------------------------------------------------------------**
    **    DOORBELLn Interrupt Condition Routing Register (DOORBELLn_ICRR) **
    **--------------------------------------------------------------------*/

    /*Route all DOORBELL interrupts to intdst1 [or EVENT 21 refer table in section Interrupt Sources 
    and Interrupt Controller of 6455/6482 datasheet]*/

        SRIO_REGS->DOORBELL_INTR_ROUTE[0].DOORBELL_ICRR 	= 0x11111111;      
    SRIO_REGS->DOORBELL_INTR_ROUTE[0].DOORBELL_ICRR2 	= 0x11111111;      

        SRIO_REGS->DOORBELL_INTR_ROUTE[1].DOORBELL_ICRR 	= 0x11111111;     
    SRIO_REGS->DOORBELL_INTR_ROUTE[1].DOORBELL_ICRR2	= 0x11111111;   

        SRIO_REGS->DOORBELL_INTR_ROUTE[2].DOORBELL_ICRR 	= 0x11111111;   
    SRIO_REGS->DOORBELL_INTR_ROUTE[2].DOORBELL_ICRR2	= 0x11111111;  

        SRIO_REGS->DOORBELL_INTR_ROUTE[3].DOORBELL_ICRR 	= 0x11111111;   
    SRIO_REGS->DOORBELL_INTR_ROUTE[3].DOORBELL_ICRR2	= 0x11111111; 



    /*-------------------------------------------------------------------------------------------------------**
    **     RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) & TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) **
    **-------------------------------------------------------------------------------------------------------*/
    SRIO_REGS->TX_CPPI_ICCR		= 0xFFFFFFFF;     
    SRIO_REGS->RX_CPPI_ICCR		= 0xFFFFFFFF;     

    /*------------------------------------------------------------------**
    **     TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) **
    **     RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) **
    **------------------------------------------------------------------*/
    /* NOT ROUTED */
    SRIO_REGS->TX_CPPI_ICRR		= 0xFFFFFFFF;      
    SRIO_REGS->TX_CPPI_ICRR2  	= 0xFFFFFFFF;     
    SRIO_REGS->RX_CPPI_ICRR    	= 0xFFFFFFFF;    
    SRIO_REGS->RX_CPPI_ICRR2   	= 0xFFFFFFFF;    

    /*-----------------------------------------------------------------------------------**
    **     Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR). **
    **-----------------------------------------------------------------------------------*/

        SRIO_REGS->ERR_RST_EVNT_ICCR  = 0xFFFFFFFF;    

    /*--------------------------------------------------------------------------**
    **     Error, Reset, and Special Event Interrupt Condition Routing Register **
    **     SRIO Registers(ERR_RST_EVNT_ICRR)                                    **
    **--------------------------------------------------------------------------*/

    /*Route Multi-cast event control symbol interrupt received on any port to to intdst4 [or EVENT 22 refer table in section Interrupt Sources 
    and Interrupt Controller of 6455/6482 datasheet]*/
    SRIO_REGS->ERR_RST_EVNT_ICRR  = 0x00000FF4;
    SRIO_REGS->ERR_RST_EVNT_ICRR2 = 0x0000FFFF;
    SRIO_REGS->ERR_RST_EVNT_ICRR3 = 0x0000000F;



    /*--------------------------------------------------------**
    ** 	 Peripheral Settings Control Register (PER_SET_CNTL). **
    **--------------------------------------------------------*/
    wdata =	CSL_FMKT(SRIO_PER_SET_CNTL_BOOT_COMPLETE,WRITE_ENABLE);
    mask  = CSL_MMK(SRIO_PER_SET_CNTL_BOOT_COMPLETE);
    rdata = SRIO_REGS->PER_SET_CNTL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->PER_SET_CNTL	= mdata ;  


    /* Enabled above to write to read only register fields in the SRIO space.*/

        SRIO_REGS->DEV_ID     = CSL_SRIO_DEV_ID_RESETVAL     ;  
    SRIO_REGS->DEV_INFO	  = CSL_SRIO_DEV_INFO_RESETVAL   ;  
    SRIO_REGS->ASBLY_ID	  = CSL_SRIO_ASBLY_ID_RESETVAL   ;  
    SRIO_REGS->ASBLY_INFO = CSL_SRIO_ASBLY_INFO_RESETVAL ;

    /* Note : Previously written value was 0x20000119, writing a 1 to reserved space*/
    SRIO_REGS->PE_FEAT = CSL_SRIO_PE_FEAT_RESETVAL | \
        CSL_FMK(SRIO_PE_FEAT_LARGE_SUPPORT, 1);

    /* This is the Switch Port Information CAR (Configuration Space Offset 0x14).
    This register defines the switching capabilities of a processing element*/
    rdata = SRIO_REGS->RSVD28[0];
    wdata = 0x00000400;
    mask  = 0x0000FF00;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->RSVD28[0]		 		= mdata ;  // 4 ports

    wdata =	CSL_FMK(SRIO_SRC_OP_READ,1)            | \
        CSL_FMK(SRIO_SRC_OP_WRITE,1)           | \
        CSL_FMK(SRIO_SRC_OP_STREAM_WRITE,1)    | \
        CSL_FMK(SRIO_SRC_OP_WRITE_WITH_RESP,1) | \
        CSL_FMK(SRIO_SRC_OP_DATA_MESS,1)       | \
        CSL_FMK(SRIO_SRC_OP_DOORBELL,1)        | \
        CSL_FMK(SRIO_SRC_OP_PORT_WRITE,1);

        mask  = CSL_MMK(SRIO_SRC_OP_READ)              |\
        CSL_MMK(SRIO_SRC_OP_WRITE)             |\
        CSL_MMK(SRIO_SRC_OP_STREAM_WRITE)      |\
        CSL_MMK(SRIO_SRC_OP_WRITE_WITH_RESP)   |\
        CSL_MMK(SRIO_SRC_OP_DATA_MESS)         |\
        CSL_MMK(SRIO_SRC_OP_DOORBELL)          |\
        CSL_MMK(SRIO_SRC_OP_PORT_WRITE);

        rdata = SRIO_REGS->SRC_OP;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SRC_OP		 		= mdata ;  // all



    wdata =	CSL_FMK(SRIO_DEST_OP_READ,1)            | \
        CSL_FMK(SRIO_DEST_OP_WRITE,1)           | \
        CSL_FMK(SRIO_DEST_OP_STREAM_WRITE,1)    | \
        CSL_FMK(SRIO_DEST_OP_WRITE_WITH_RESP,1) | \
        CSL_FMK(SRIO_DEST_OP_DATA_MESS,1)       | \
        CSL_FMK(SRIO_DEST_OP_DOORBELL,1)        | \
        CSL_FMK(SRIO_DEST_OP_PORT_WRITE,1);

        mask  = CSL_MMK(SRIO_DEST_OP_READ)              |\
        CSL_MMK(SRIO_DEST_OP_WRITE)             |\
        CSL_MMK(SRIO_DEST_OP_STREAM_WRITE)      |\
        CSL_MMK(SRIO_DEST_OP_WRITE_WITH_RESP)   |\
        CSL_MMK(SRIO_DEST_OP_DATA_MESS)         |\
        CSL_MMK(SRIO_DEST_OP_DOORBELL)          |\
        CSL_MMK(SRIO_DEST_OP_PORT_WRITE);

        rdata = SRIO_REGS->DEST_OP;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->DEST_OP		 		= mdata ;  // all except atomic

    CSL_FINST(SRIO_REGS->PE_LL_CTL, SRIO_PE_LL_CTL_EXTENDED_ADDRESSING_CONTROL, 34BIT);


        SRIO_REGS->LCL_CFG_HBAR = 0x00000000 ;  
    rdata = SRIO_REGS->LCL_CFG_BAR;
    wdata = 0x00000000;
    mask  = 0xFFFFC000;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->LCL_CFG_BAR = mdata ;  // 0



    wdata = (Uint32) CSL_FMK(SRIO_BASE_ID_BASE_DEVICEID,pInitOptions->smallDevId)   | \
        CSL_FMK(SRIO_BASE_ID_LARGE_BASE_DEVICEID,pInitOptions->largeDevId);

        mask  = CSL_MMK(SRIO_BASE_ID_BASE_DEVICEID)    | \
        CSL_MMK(SRIO_BASE_ID_LARGE_BASE_DEVICEID);

    rdata = SRIO_REGS->BASE_ID;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->BASE_ID		 		= mdata ;  

    /*-------------------------------------------------**
    **     Port-Write Target Device ID CSR (PW_TGT_ID) **
    **-------------------------------------------------*/
    wdata = pInitOptions->smallDevId;
    SRIO_REGS->PW_TGT_ID            = (wdata << 16) & 0xFFFF0000;

    /*     rdata = SRIO_REGS->HOST_BASE_ID_LOCK;     */
    /*     wdata = 0x00000000;                       */
    /*     mask  = 0x0000FFFF;                       */
    /*     mdata = (wdata & mask) | (rdata & ~mask); */
    /*     SRIO_REGS->HOST_BASE_ID_LOCK	= mdata ;    */

    /*---------------------------------------------------------------**
    **    Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) **
    **---------------------------------------------------------------*/

    wdata = CSL_FMK(SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER,(Uint32)9)   | \
        CSL_FMK(SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER,0);

    mask  = CSL_MMK(SRIO_SP_IP_DISCOVERY_TIMER_DISCOVERY_TIMER)    | \
        CSL_MMK(SRIO_SP_IP_DISCOVERY_TIMER_PW_TIMER);

    rdata = SRIO_REGS->SP_IP_DISCOVERY_TIMER;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SP_IP_DISCOVERY_TIMER		= mdata ;  // 0, short cycles for sim


    /*-----------------------------------**
    **  Port IP Mode CSR (SP_IP_MODE)    **
    **-----------------------------------*/
    if (srio_4P_1X_Mode)
    {
        wdata  =  CSL_FMK(SRIO_SP_IP_MODE_SP_MODE,1);
    }
    else
    {
        wdata  =  CSL_FMK(SRIO_SP_IP_MODE_SP_MODE,0);
    }

    wdata  |= CSL_FMK(SRIO_SP_IP_MODE_TGT_ID_DIS,1)           |\
        CSL_FMKT(SRIO_SP_IP_MODE_IDLE_ERR_DIS,ENABLE)   | \
        CSL_FMKT(SRIO_SP_IP_MODE_TX_FIFO_BYPASS,DISABLE)| \
        CSL_FMKT(SRIO_SP_IP_MODE_PW_DIS,DISABLE);

    mask  = CSL_MMK(SRIO_SP_IP_MODE_SP_MODE)        | \
        CSL_MMK(SRIO_SP_IP_MODE_TGT_ID_DIS)     | \
        CSL_MMK(SRIO_SP_IP_MODE_IDLE_ERR_DIS)   | \
        CSL_MMK(SRIO_SP_IP_MODE_TX_FIFO_BYPASS) | \
        CSL_MMK(SRIO_SP_IP_MODE_PW_DIS);

        rdata = SRIO_REGS->SP_IP_MODE;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SP_IP_MODE = mdata ;  

    /*--------------------------------------------**
    **     Serial Port IP Prescalar (IP_PRESCAL). **
    **--------------------------------------------*/
    wdata  = CSL_FMK(SRIO_IP_PRESCAL_PRESCALE,0x21);
    mask   = CSL_MMK(SRIO_IP_PRESCAL_PRESCALE);
    rdata = SRIO_REGS->IP_PRESCAL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->IP_PRESCAL		= mdata ;  // srv_clk prescalar=0x21 (333MHz)


    /*----------------------------------------------**
    **     Port Silence Timer n (SPn_SILENCE_TIMER) **
    **----------------------------------------------*/
    wdata  = CSL_FMK(SRIO_SP_SILENCE_TIMER_SILENCE_TIMER,CSL_SRIO_SP_SILENCE_TIMER_RESETVAL);
    mask   = CSL_MMK(SRIO_SP_SILENCE_TIMER_SILENCE_TIMER);

    /* Update for four ports*/
    for (i=0;i < 4; i++)
    {
        rdata = SRIO_REGS->PORT_OPTION[i].SP_SILENCE_TIMER;
        mdata = (wdata & mask) | (rdata & ~mask);
        SRIO_REGS->PORT_OPTION[i].SP_SILENCE_TIMER = mdata ;  // 0, short cycles for sim        
    }

    /*--------------------------------------------------------**
    ** 	 Peripheral Settings Control Register (PER_SET_CNTL). **
    **--------------------------------------------------------*/
    wdata =	CSL_FMKT(SRIO_PER_SET_CNTL_BOOT_COMPLETE,WRITE_DISABLE);
    mask  = CSL_MMK(SRIO_PER_SET_CNTL_BOOT_COMPLETE);
    rdata = SRIO_REGS->PER_SET_CNTL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->PER_SET_CNTL	= mdata ;  

    /*------------------------------------------------**
    **     Port Link Time-Out Control CSR (SP_LT_CTL) **
    **------------------------------------------------*/
    wdata =	CSL_FMK(SRIO_SP_LT_CTL_TIMEOUT_VALUE,0x00000F); //3.1 us
    mask  = CSL_MMK(SRIO_SP_LT_CTL_TIMEOUT_VALUE);

    rdata = SRIO_REGS->SP_LT_CTL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SP_LT_CTL  		= mdata ;  // 3.1us

    /*----------------------------------------------------**
    **     Port Response Time-Out Control CSR (SP_RT_CTL) **
    **----------------------------------------------------*/
    wdata =	(Uint32)CSL_FMK(SRIO_SP_RT_CTL_TIMEOUT_VALUE,(Uint32)0x64); //6 seconds
    mask  = CSL_MMK(SRIO_SP_RT_CTL_TIMEOUT_VALUE);
    rdata = SRIO_REGS->SP_RT_CTL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SP_RT_CTL 		= mdata ;  // 3.1us

    /*-------------------------------------------**
    **     Port General Control CSR (SP_GEN_CTL) **
    **-------------------------------------------*/

    wdata  = (Uint32) CSL_FMK(SRIO_SP_GEN_CTL_HOST,(Uint32)1)           |\
        CSL_FMK(SRIO_SP_GEN_CTL_MASTER_ENABLE,1)  | \
        CSL_FMK(SRIO_SP_GEN_CTL_DISCOVERED,0);

    mask  = CSL_MMK(SRIO_SP_GEN_CTL_HOST)           | \
        CSL_MMK(SRIO_SP_GEN_CTL_MASTER_ENABLE)  | \
        CSL_MMK(SRIO_SP_GEN_CTL_DISCOVERED);

    rdata = SRIO_REGS->SP_GEN_CTL;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SP_GEN_CTL 		= mdata ;  // agent, master, undiscovered

    /*----------------------------------**
    **     Port Control CSR n (SPn_CTL) **
    **----------------------------------*/

    wdata  =  CSL_FMK(SRIO_SP_CTL_INPUT_PORT_ENABLE,1)           |\
        CSL_FMK(SRIO_SP_CTL_OUTPUT_PORT_ENABLE,1);

    mask  = CSL_MMK(SRIO_SP_CTL_INPUT_PORT_ENABLE)           | \
        CSL_MMK(SRIO_SP_CTL_OUTPUT_PORT_ENABLE) ;

    for (i=0;i < 4; i++)
    {
        rdata = SRIO_REGS->PORT[i].SP_CTL;
        mdata = (wdata & mask) | (rdata & ~mask);
        SRIO_REGS->PORT[i].SP_CTL	= mdata ;  // enable i/o
    }


    /*     rdata = SRIO_REGS->ERR_RPT_BH;                                       */
    /*     wdata = 0x00000000;                                                  */
    /*     mask  = 0x00000000;                                                  */
    /*     mdata = (wdata & mask) | (rdata & ~mask);                            */
    /*     SRIO_REGS->ERR_RPT_BH	 		= mdata ;  // next ext=0x0000(last) */

    SRIO_REGS->ERR_DET	 			= 0x00000000 ;  // clear
    SRIO_REGS->ERR_EN		 		= 0x00000000 ;  // disable
    SRIO_REGS->H_ADDR_CAPT	 		= 0x00000000 ;  // clear
    SRIO_REGS->ADDR_CAPT		 	= 0x00000000 ;  // clear
    SRIO_REGS->ID_CAPT		 		= 0x00000000 ;  // clear
    SRIO_REGS->CTRL_CAPT		 	= 0x00000000 ;  // clear
    SRIO_REGS->SP_IP_PW_IN_CAPT[0]	= 0x00000000 ;  // clear
    SRIO_REGS->SP_IP_PW_IN_CAPT[1]	= 0x00000000 ;  // clear
    SRIO_REGS->SP_IP_PW_IN_CAPT[2]	= 0x00000000 ;  // clear
    SRIO_REGS->SP_IP_PW_IN_CAPT[3]	= 0x00000000 ;  // clear

    /*-----------------------------------**
    **     Port IP Mode CSR (SP_IP_MODE) **
    **-----------------------------------*/
    rdata = SRIO_REGS->SP_IP_MODE;
    wdata = 0x0000003F;
    mask  = 0x0000003F;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->SP_IP_MODE = mdata ;  

    /* POLL for PORT_OK Status*/

    rdata = CSL_FEXT(SRIO_REGS->PORT[0].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
    while (!rdata)
    {
        rdata = CSL_FEXT(SRIO_REGS->PORT[0].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
    }
    // dump_Sp_Err_Stat_Register(0);          

    if (srio_4P_1X_Mode)
    {

        rdata = CSL_FEXT(SRIO_REGS->PORT[1].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        while (!rdata)
        {
            rdata = CSL_FEXT(SRIO_REGS->PORT[1].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        }

        // dump_Sp_Err_Stat_Register(1);          

        rdata = CSL_FEXT(SRIO_REGS->PORT[2].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        while (!rdata)
        {
            rdata = CSL_FEXT(SRIO_REGS->PORT[2].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        }

        // dump_Sp_Err_Stat_Register(2);          

        rdata = CSL_FEXT(SRIO_REGS->PORT[3].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        while (!rdata)
        {
            rdata = CSL_FEXT(SRIO_REGS->PORT[3].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        }
        // dump_Sp_Err_Stat_Register(3);          
    }

    /*---------------------------------------**
    **  Peripheral Control Register (PCR)    **
    **---------------------------------------*/
    wdata  = CSL_FMK(SRIO_PCR_PEREN,1);
    mask   = CSL_MMK(SRIO_PCR_PEREN) ;

    rdata = SRIO_REGS->PCR;
    mdata = (wdata & mask) | (rdata & ~mask);
    SRIO_REGS->PCR = mdata ;  // peren


    waitusec(100000);


#if 1

    /*-----------------------------------------------------------------**
    **     Do a remote Port Reset to clear and start with ACK_ID of 0. **
    **-----------------------------------------------------------------*/
    if (enablePeerReset)
    {
        
        force_Remote_Port_Reset(0);

        if (srio_4P_1X_Mode)
        {
            force_Remote_Port_Reset(1);
            force_Remote_Port_Reset(2);
            force_Remote_Port_Reset(3);
        }

        waitusec(10000);
        waitusec(10000);
        waitusec(10000);
        waitusec(10000);

        /* POLL for PORT_OK Status*/
        rdata = CSL_FEXT(SRIO_REGS->PORT[0].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        while (!rdata)
        {
            rdata = CSL_FEXT(SRIO_REGS->PORT[0].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
        }
        // dump_Sp_Err_Stat_Register(0);          

        if (srio_4P_1X_Mode)
        {

            rdata = CSL_FEXT(SRIO_REGS->PORT[1].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
            while (!rdata)
            {
                rdata = CSL_FEXT(SRIO_REGS->PORT[1].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
            }

            // dump_Sp_Err_Stat_Register(1);          

            rdata = CSL_FEXT(SRIO_REGS->PORT[2].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
            while (!rdata)
            {
                rdata = CSL_FEXT(SRIO_REGS->PORT[2].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
            }

            // dump_Sp_Err_Stat_Register(2);          

            rdata = CSL_FEXT(SRIO_REGS->PORT[3].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
            while (!rdata)
            {
                rdata = CSL_FEXT(SRIO_REGS->PORT[3].SP_ERR_STAT, SRIO_SP_ERR_STAT_PORT_OK);
            }
            // dump_Sp_Err_Stat_Register(3);          
        }

        waitusec(100000);
    }

#endif

    /* To clear any recoverable errors after getting port OK*/
    SRIO_REGS->PORT[0].SP_ERR_STAT = 0xFFFFFFFF;
    SRIO_REGS->PORT[1].SP_ERR_STAT = 0xFFFFFFFF;
    SRIO_REGS->PORT[2].SP_ERR_STAT = 0xFFFFFFFF;
    SRIO_REGS->PORT[3].SP_ERR_STAT = 0xFFFFFFFF;
      

    waitusec(100000);
 

#if 1


    /*-------------------------------------------------**
    **     Error recovery  to clear any stopped state. **
    **-------------------------------------------------*/
    if (is_SRIO_Port_Error(0) || \
    is_SRIO_Port_Input_Stopped(0) || \
    is_SRIO_Port_Output_Stopped(0))
    {
        clear_Srio_Stopped_State_Error(0);
        waitusec(10000);
        // dump_Sp_Err_Stat_Register(0);          
    }


    if (srio_4P_1X_Mode){

        if (is_SRIO_Port_Error(1) || \
            is_SRIO_Port_Input_Stopped(1) || \
            is_SRIO_Port_Output_Stopped(1))
        {
            clear_Srio_Stopped_State_Error(1);
            waitusec(10000);
            // dump_Sp_Err_Stat_Register(1);          
        }

        if (is_SRIO_Port_Error(2) || \
            is_SRIO_Port_Input_Stopped(2) || \
            is_SRIO_Port_Output_Stopped(2))
        {
            clear_Srio_Stopped_State_Error(2);
            waitusec(10000);
            // dump_Sp_Err_Stat_Register(2);          
        }

        if (is_SRIO_Port_Error(3) || \
            is_SRIO_Port_Input_Stopped(3) || \
            is_SRIO_Port_Output_Stopped(3))
        {
            clear_Srio_Stopped_State_Error(3);
            waitusec(10000);
            // dump_Sp_Err_Stat_Register(3);          
        }
    }


#endif


    waitusec(100000);
   
    // dump_Sp_Err_Stat_Register(0);          
    // dump_Sp_Err_Stat_Register(1);          
    // dump_Sp_Err_Stat_Register(2);          
    // dump_Sp_Err_Stat_Register(3);          
 
    return 1;

}