root@6530a5cb9657:/home/root/examples/osrt_python/advanced_examples/unit_tests_validation/ort# python3 ./onnxrt_ep.py -m gridsample
['gridsample']
Available execution providers :  ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']

Running 1 Models - ['gridsample']


Running_Model :  gridsample  

libtidl_onnxrt_EP loaded 0x5b4854dce2e0 
artifacts_folder                                = ../model-artifacts//gridsample/artifacts 
debug_level                                     = 4 
target_priority                                 = 0 
max_pre_empt_delay                              = 340282346638528859811704183484516925440.000000 
Final number of subgraphs created are : 1, - Offloaded Nodes - 2, Total Nodes - 2 
In TIDL_createStateInfer 
Compute on node : TIDLExecutionProvider_TIDL_0_0
************ in TIDL_subgraphRtCreate ************ 
 The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
 0.0s:  VX_ZONE_INIT:Enabled
 0.10s:  VX_ZONE_ERROR:Enabled
 0.13s:  VX_ZONE_WARNING:Enabled
 0.2744s:  VX_ZONE_INIT:[tivxInit:190] Initialization Done !!!
************ TIDL_subgraphRtCreate done ************ 
 *******   In TIDL_subgraphRtInvoke  ******** 
   0         1.00000        -3.04614         3.17097 6
   2        32.00000        -3.03125         3.15625 1
   4        49.71195        -2.09205         1.91101 1
   1         1.00000        -3.11686         3.80166 6
   3     32768.00000        -1.00000         0.99997 3
   5        49.71195        -1.46846         1.10637 1
   6         1.00000        -1.46846         1.10637 6
 Layer,   Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger,    paddingWait,LayerWithoutPad,LayerHandleCopy,   BackupCycles,  RestoreCycles,Multic7xContextCopyCycles,
     2,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     4,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     3,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     5,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
     6,              0,              0,              0,              0,              0,                 0,              0,                 0,              0,              0,              0,              0,              0,              0,              0,              0,              0,
 Sum of Layer Cycles 0 
Sub Graph Stats 14.000000 24000.000000 104.000000 
*******  TIDL_subgraphRtInvoke done  ******** 
Completed model -  gridsample.onnx

 
Name : gridsample                                        , Total time :      24.07, Offload Time :      24.00 , DDR RW MBs : 0
 
 
************ in TIDL_subgraphRtDelete ************ 
 MEM: Deinit ... !!!
MEM: Alloc's: 28 alloc's of 75485531 bytes 
MEM: Free's : 28 free's  of 75485531 bytes 
MEM: Open's : 0 allocs  of 0 bytes 
MEM: Deinit ... Done !!!