#define CM_FCLKEN1_CORE_ADDR    0x48004a00
#define CM_ICLKEN1_CORE_ADDR	0x48004a10


/* Control register */
#define CONTROL_PADCONF_START   0x48002030
/* MUX register */
#define GPT11_MUX_OFFSET        (0x480021DC - CONTROL_PADCONF_START)
#define PWM_ENABLE_MUX          0x0001

/* Clock register */
#define CLOCK_CONTROL_REG_CM_START	0x48004A00
#define CM_CLKSEL_CORE_OFFSET		0x40

/* GPT11 register */
#define GPT11_CTL_BASE          0x48088000


/* GPT register offsets */
#define GPT_TIOCP_CFG 0x010
#define GPT_TISTAT    0x014
#define GPT_TCLR      0x024
#define GPT_TCRR      0x028
#define GPT_TLDR      0x02C
#define GPT_TTGR      0x030
#define GPT_TMAR      0x038
#define GPT_TSICR     0x040

/*This register controls optional features specific to the timer functionality*/
/* TCLR bits for PWM */
#define GPT_TCLR_ST             (1 << 0)	/* stop/start */
#define GPT_TCLR_AR             (1 << 1)	/* one shot/auto-reload */
#define GPT_TCLR_CE             (1 << 6)	/* disable/enable compare */
#define GPT_TCLR_TRG_OVFL_MATCH	(2 << 10)	/* trigger on overflow and match */
#define GPT_TCLR_PT             (1 << 12)	/* pulse/toggle modulation */


/*// bitmask defines for TIOCP_CFG*/
#define EMUFREE         (0x00000020)   /*// bit 5*/
#define SOFTRESET       (0x00000002)   /*// bit 1*/

/*// bitmask defines for TSICR*/
#define SFT             (0x00000002)   /*// bit 1*/


/*OVF_Rate = (0xFFFF FFFF - GPTn.TLDR + 1) * (timer-functional clock period) * PS
For TLDR = 0xFFFFFF00 and PS=1(as no prescaler used) with clk=32kHz
the
OVF_Rate = 8ms
*/
#define DEFAULT_TLDR            0xFFFFFE00      /*TLDR : The value of the timer load register*/

/* default 50% duty cycle */
#define DEFAULT_DUTY_CYCLE      50
#define DEFAULT_TMAR            (DEFAULT_TLDR + (0xFFFFFFFF - DEFAULT_TLDR - 1) * DEFAULT_DUTY_CYCLE / 100)

/* default TCLR is off state */
#define DEFAULT_TCLR            ( GPT_TCLR_PT | GPT_TCLR_TRG_OVFL_MATCH | GPT_TCLR_CE | GPT_TCLR_AR )



void udAm35xxLcdPwmSetDutyCycle(unsigned int duty_cycle1)
{
   uint32_t tldr, tmar, tclr;
   uint32_t new_tmar;

   tldr = DEFAULT_TLDR; /*TLDR : The value of the timer load register.*/
   new_tmar = (duty_cycle1 * num_settings) / 100;
   if (new_tmar < 1)
      new_tmar = 1;
   else if (new_tmar > num_settings)
      new_tmar = num_settings;

   tmar = tldr + new_tmar;
   UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TMAR, tmar);
   UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TCRR, tmar);
   udAm35xxLcdPwmEnableClock();
   tclr = DEFAULT_TCLR;
   tclr |= GPT_TCLR_ST;
   UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TCLR, tclr);
}



void udAm35xxLcdPwmInit(void)
{
    AM35XXSETBIT(CONTROL_PADCONF_START+GPT11_MUX_OFFSET, PWM_ENABLE_MUX);

    /*GPTIMER 11 functional clock is enabled*/
    AM35XXSETBIT(CM_FCLKEN1_CORE_ADDR, (0x01 << 12));

    /*GPTIMER 11 interface clock is enabled*/
    AM35XXSETBIT(CM_ICLKEN1_CORE_ADDR, (0x01 << 12));

    /*CLKSEL_GPT11: source is CM_32K_CLK*/
    AM35XXCLRBIT((CLOCK_CONTROL_REG_CM_START+CM_CLKSEL_CORE_OFFSET), (1 << 7));

    uint32_t tldr, tmar, tclr;
    uint32_t new_tmar;

    /*******************Reset the timer registers***************/
    AM35XXSETBIT(GPT11_CTL_BASE + GPT_TIOCP_CFG, SOFTRESET);
    while (!UGL_AM35XX_READ_REG32(GPT11_CTL_BASE + GPT_TISTAT));

    AM35XXSETBIT(GPT11_CTL_BASE + GPT_TSICR, SFT);
    while (!UGL_AM35XX_READ_REG32(GPT11_CTL_BASE + GPT_TISTAT));

    AM35XXSETBIT(GPT11_CTL_BASE + GPT_TIOCP_CFG, EMUFREE);
    /***********************************************************/

    /*Clear timer load and timer trigger registers */
    UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TLDR, 0);
    UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TTGR, 0x1);

    tldr = DEFAULT_TLDR;
    tclr &= ~GPT_TCLR_ST;
    UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TCLR,tclr );

    num_settings = 0xFFFFFFFE - tldr;
    UGL_AM35XX_WRITE_REG32(GPT11_CTL_BASE + GPT_TLDR, tldr);	

    udAm35xxLcdPwmSetDutyCycle(DEFAULT_DUTY_CYCLE);
}