root@j7200-iwg52m:~# root@j7200-iwg52m:~# k3conf dump clocks | grep -i serdes | 19 | 3 | DEV_CPSW0_SERDES4_RXCLK | CLK_STATE_READY | 0 | | 19 | 14 | DEV_CPSW0_SERDES4_RXFCLK | CLK_STATE_READY | 0 | | 19 | 32 | DEV_CPSW0_SERDES1_TXCLK | CLK_STATE_READY | 0 | | 19 | 34 | DEV_CPSW0_SERDES2_RXCLK | CLK_STATE_READY | 0 | | 19 | 35 | DEV_CPSW0_SERDES1_RXFCLK | CLK_STATE_READY | 0 | | 19 | 37 | DEV_CPSW0_SERDES1_TXMCLK | CLK_STATE_READY | 0 | | 19 | 38 | DEV_CPSW0_SERDES1_REFCLK | CLK_STATE_READY | 0 | | 19 | 42 | DEV_CPSW0_SERDES3_TXFCLK | CLK_STATE_READY | 0 | | 19 | 43 | DEV_CPSW0_SERDES3_RXFCLK | CLK_STATE_READY | 0 | | 19 | 46 | DEV_CPSW0_SERDES2_TXCLK | CLK_STATE_READY | 0 | | 19 | 47 | DEV_CPSW0_SERDES1_RXCLK | CLK_STATE_READY | 0 | | 19 | 48 | DEV_CPSW0_SERDES1_TXFCLK | CLK_STATE_READY | 0 | | 19 | 50 | DEV_CPSW0_SERDES2_TXFCLK | CLK_STATE_READY | 0 | | 19 | 54 | DEV_CPSW0_SERDES4_TXMCLK | CLK_STATE_READY | 0 | | 19 | 55 | DEV_CPSW0_SERDES3_TXCLK | CLK_STATE_READY | 0 | | 19 | 56 | DEV_CPSW0_SERDES2_TXMCLK | CLK_STATE_READY | 0 | | 19 | 58 | DEV_CPSW0_SERDES4_REFCLK | CLK_STATE_READY | 0 | | 19 | 59 | DEV_CPSW0_SERDES3_TXMCLK | CLK_STATE_READY | 0 | | 19 | 60 | DEV_CPSW0_SERDES2_REFCLK | CLK_STATE_READY | 0 | | 19 | 61 | DEV_CPSW0_SERDES3_REFCLK | CLK_STATE_READY | 0 | | 19 | 62 | DEV_CPSW0_SERDES3_RXCLK | CLK_STATE_READY | 0 | | 19 | 64 | DEV_CPSW0_SERDES2_RXFCLK | CLK_STATE_READY | 0 | | 19 | 66 | DEV_CPSW0_SERDES4_TXCLK | CLK_STATE_READY | 0 | | 19 | 67 | DEV_CPSW0_SERDES4_TXFCLK | CLK_STATE_READY | 0 | | 292 | 1 | DEV_SERDES_10G1_IP3_LN1_TXFCLK | CLK_STATE_READY | 0 | | 292 | 3 | DEV_SERDES_10G1_IP2_LN2_REFCLK | CLK_STATE_READY | 0 | | 292 | 4 | DEV_SERDES_10G1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 | | 292 | 6 | DEV_SERDES_10G1_IP3_LN3_RXCLK | CLK_STATE_READY | 0 | | 292 | 9 | DEV_SERDES_10G1_IP2_LN2_RXCLK | CLK_STATE_READY | 0 | | 292 | 10 | DEV_SERDES_10G1_IP1_LN0_TXFCLK | CLK_STATE_READY | 0 | | 292 | 11 | DEV_SERDES_10G1_CLK | CLK_STATE_READY | 125000000 | | 292 | 13 | DEV_SERDES_10G1_IP1_LN3_RXCLK | CLK_STATE_READY | 0 | | 292 | 14 | DEV_SERDES_10G1_IP1_LN1_TXMCLK | CLK_STATE_READY | 0 | | 292 | 15 | DEV_SERDES_10G1_IP2_LN0_TXFCLK | CLK_STATE_READY | 0 | | 292 | 16 | DEV_SERDES_10G1_IP2_LN2_TXMCLK | CLK_STATE_READY | 0 | | 292 | 19 | DEV_SERDES_10G1_IP3_LN1_TXCLK | CLK_STATE_READY | 0 | | 292 | 21 | DEV_SERDES_10G1_IP2_LN3_RXFCLK | CLK_STATE_READY | 0 | | 292 | 22 | DEV_SERDES_10G1_IP1_LN2_TXCLK | CLK_STATE_READY | 0 | | 292 | 24 | DEV_SERDES_10G1_IP2_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 25 | DEV_SERDES_10G1_IP2_LN1_TXCLK | CLK_STATE_READY | 0 | | 292 | 29 | DEV_SERDES_10G1_IP1_LN2_TXMCLK | CLK_STATE_READY | 0 | | 292 | 32 | DEV_SERDES_10G1_IP2_LN1_TXMCLK | CLK_STATE_READY | 0 | | 292 | 33 | DEV_SERDES_10G1_IP2_LN1_TXFCLK | CLK_STATE_READY | 0 | | 292 | 34 | DEV_SERDES_10G1_IP1_LN1_TXFCLK | CLK_STATE_READY | 0 | | 292 | 38 | DEV_SERDES_10G1_IP1_LN2_RXCLK | CLK_STATE_READY | 0 | | 292 | 40 | DEV_SERDES_10G1_IP2_LN1_REFCLK | CLK_STATE_READY | 0 | | 292 | 41 | DEV_SERDES_10G1_IP2_LN0_TXMCLK | CLK_STATE_READY | 0 | | 292 | 42 | DEV_SERDES_10G1_IP2_LN3_RXCLK | CLK_STATE_READY | 0 | | 292 | 43 | DEV_SERDES_10G1_IP2_LN2_TXCLK | CLK_STATE_READY | 0 | | 292 | 44 | DEV_SERDES_10G1_IP2_LN2_RXFCLK | CLK_STATE_READY | 0 | | 292 | 45 | DEV_SERDES_10G1_IP1_LN1_RXFCLK | CLK_STATE_READY | 0 | | 292 | 49 | DEV_SERDES_10G1_IP1_LN0_RXCLK | CLK_STATE_READY | 0 | | 292 | 52 | DEV_SERDES_10G1_IP1_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 55 | DEV_SERDES_10G1_IP1_LN0_RXFCLK | CLK_STATE_READY | 0 | | 292 | 56 | DEV_SERDES_10G1_IP3_LN3_TXCLK | CLK_STATE_READY | 0 | | 292 | 59 | DEV_SERDES_10G1_IP2_LN3_REFCLK | CLK_STATE_READY | 0 | | 292 | 61 | DEV_SERDES_10G1_IP2_LN0_TXCLK | CLK_STATE_READY | 0 | | 292 | 62 | DEV_SERDES_10G1_IP2_LN3_TXMCLK | CLK_STATE_READY | 0 | | 292 | 63 | DEV_SERDES_10G1_IP1_LN1_REFCLK | CLK_STATE_READY | 0 | | 292 | 65 | DEV_SERDES_10G1_IP1_LN3_TXCLK | CLK_STATE_READY | 0 | | 292 | 66 | DEV_SERDES_10G1_IP3_LN1_TXMCLK | CLK_STATE_READY | 0 | | 292 | 67 | DEV_SERDES_10G1_IP2_LN2_TXFCLK | CLK_STATE_READY | 0 | | 292 | 73 | DEV_SERDES_10G1_IP3_LN1_RXCLK | CLK_STATE_READY | 0 | | 292 | 74 | DEV_SERDES_10G1_IP3_LN1_REFCLK | CLK_STATE_READY | 0 | | 292 | 75 | DEV_SERDES_10G1_IP1_LN3_REFCLK | CLK_STATE_READY | 0 | | 292 | 77 | DEV_SERDES_10G1_IP1_LN0_REFCLK | CLK_STATE_READY | 0 | | 292 | 80 | DEV_SERDES_10G1_IP1_LN2_REFCLK | CLK_STATE_READY | 0 | | 292 | 81 | DEV_SERDES_10G1_IP2_LN0_REFCLK | CLK_STATE_READY | 0 | | 292 | 82 | DEV_SERDES_10G1_IP2_LN0_RXCLK | CLK_STATE_READY | 0 | | 292 | 85 | DEV_SERDES_10G1_CORE_REF_CLK | CLK_STATE_READY | 156250000 | | 292 | 86 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_GLUELOGIC_HFOSC0_CLKOUT | CLK_STATE_READY | 19200000 | | 292 | 87 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_BOARD_0_HFOSC1_CLK_OUT | CLK_STATE_READY | 0 | | 292 | 88 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_3_HSDIVOUT4_CLK | CLK_STATE_READY | 156250000 | | 292 | 89 | DEV_SERDES_10G1_CORE_REF_CLK_PARENT_HSDIV4_16FFT_MAIN_2_HSDIVOUT4_CLK | CLK_STATE_READY | 100000000 | | 292 | 92 | DEV_SERDES_10G1_IP1_LN3_TXMCLK | CLK_STATE_READY | 0 | | 292 | 95 | DEV_SERDES_10G1_IP2_LN3_TXCLK | CLK_STATE_READY | 0 | | 292 | 96 | DEV_SERDES_10G1_IP3_LN3_RXFCLK | CLK_STATE_READY | 0 | | 292 | 98 | DEV_SERDES_10G1_IP3_LN3_REFCLK | CLK_STATE_READY | 0 | | 292 | 100 | DEV_SERDES_10G1_IP2_LN1_RXFCLK | CLK_STATE_READY | 0 | | 292 | 102 | DEV_SERDES_10G1_IP3_LN1_RXFCLK | CLK_STATE_READY | 0 | | 292 | 104 | DEV_SERDES_10G1_IP1_LN1_TXCLK | CLK_STATE_READY | 0 | | 292 | 107 | DEV_SERDES_10G1_IP3_LN3_TXFCLK | CLK_STATE_READY | 0 | | 292 | 108 | DEV_SERDES_10G1_IP1_LN3_TXFCLK | CLK_STATE_READY | 0 | | 292 | 109 | DEV_SERDES_10G1_IP2_LN3_TXFCLK | CLK_STATE_READY | 0 | | 292 | 111 | DEV_SERDES_10G1_IP1_LN0_TXCLK | CLK_STATE_READY | 0 | | 292 | 112 | DEV_SERDES_10G1_IP2_LN0_RXFCLK | CLK_STATE_READY | 0 | | 292 | 113 | DEV_SERDES_10G1_IP1_LN2_RXFCLK | CLK_STATE_READY | 0 | | 292 | 118 | DEV_SERDES_10G1_IP1_LN2_TXFCLK | CLK_STATE_READY | 0 | | 292 | 124 | DEV_SERDES_10G1_IP1_LN3_RXFCLK | CLK_STATE_READY | 0 | | 292 | 126 | DEV_SERDES_10G1_IP3_LN3_TXMCLK | CLK_STATE_READY | 0 | root@j7200-iwg52m:~# root@j7200-iwg52m:~#