/* * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ /dts-v1/; #include "am33xx.dtsi" #include #include / { model = "TI AM335x EVM"; compatible = "ti,am335x-evm", "ti,am33xx"; cpus { cpu@0 { cpu0-supply = <&vdd1_reg>; }; }; memory@80000000 { device_type = "memory"; /* +++ Seamus,512MB DDR ,20190318 ---*/ /*reg = <0x80000000 0x10000000>;*/ /* 256 MB */ reg = <0x80000000 0x20000000>; /* 512 MB */ /* --- Seamus,ramdisk ,20190318 ---*/ }; /* +++ Seamus,512MB DDR ,20190318 ---*/ chosen { bootargs = "console=ttyS0,115200n8 root=/dev/ram0"; }; /* --- Seamus,ramdisk ,20190318 ---*/ vbat: fixedregulator0 { compatible = "regulator-fixed"; regulator-name = "vbat"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; regulator-boot-on; }; lis3_reg: fixedregulator1 { compatible = "regulator-fixed"; regulator-name = "lis3_reg"; regulator-boot-on; }; #if 1 lcd_bl: backlight { compatible = "pwm-backlight"; pwms = <&ecap2 0 50000 PWM_POLARITY_INVERTED>; brightness-levels = <0 51 53 56 62 75 101 152 255>; default-brightness-level = <8>; }; panel { compatible = "ti,tilcdc,panel"; status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&lcd_pins_s0>; pinctrl-1 = <&lcd_pins_sleep>; backlight = <&lcd_bl>; enable-gpios = <&gpio1 28 0>; panel-info { ac-bias = <255>; ac-bias-intrpt = <0>; dma-burst-sz = <16>; bpp = <32>; fdd = <0x80>; sync-edge = <0>; sync-ctrl = <1>; raster-order = <0>; fifo-th = <0>; }; display-timings { 800x480 { clock-frequency = <30000000>; hactive = <800>; vactive = <480>; hfront-porch = <56>; hback-porch = <4>; hsync-len = <12>; vback-porch = <21>; vfront-porch = <16>; vsync-len = <3>; hsync-active = <0>; vsync-active = <0>; }; }; }; #endif }; /* +++ Seamus,Pinmux ,20190318 +++*/ &am33xx_pinmux { pinctrl-names = "default"; pinctrl-0 = <&InitialGPIO &clkout2_pin>; InitialGPIO: InitialGPIO { pinctrl-single,pins = < AM33XX_IOPAD(0x88C, PIN_OUTPUT | MUX_MODE7) /* GPMC_CLK.GPIO2_1 */ AM33XX_IOPAD(0x880, PIN_OUTPUT | MUX_MODE7) /* GPMC_CSn1.GPIO1_30 */ AM33XX_IOPAD(0x840, PIN_OUTPUT | MUX_MODE7) /* GPMC_A0.GPIO1_16 */ AM33XX_IOPAD(0x844, PIN_OUTPUT | MUX_MODE7) /* GPMC_A1.GPIO1_17 */ AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE7) /* GPMC_A2.GPIO1_18*/ AM33XX_IOPAD(0x84C, PIN_OUTPUT | MUX_MODE7) /* GPMC_A3.GPIO1_19 */ AM33XX_IOPAD(0x850, PIN_INPUT | MUX_MODE7) /* GPMC_A4.GPIO1_20 */ AM33XX_IOPAD(0x854, PIN_INPUT | MUX_MODE7) /* GPMC_A5.GPIO1_20 */ AM33XX_IOPAD(0x858, PIN_OUTPUT | MUX_MODE7) /* GPMC_A6.GPIO1_22 */ AM33XX_IOPAD(0x85C, PIN_OUTPUT | MUX_MODE7) /* GPMC_A7.GPIO1_23 */ AM33XX_IOPAD(0x864, PIN_INPUT | MUX_MODE7) /* GPMC_A9.GPIO1_25 */ AM33XX_IOPAD(0x868, PIN_INPUT | MUX_MODE7) /* GPMC_A10.GPIO1_26 */ AM33XX_IOPAD(0x990, PIN_OUTPUT | MUX_MODE7) /* MCASP0_ACLKX.GPIO3_14 */ AM33XX_IOPAD(0x994, PIN_OUTPUT | MUX_MODE7) /* (B13) MCASP0_FSX.GPIO3_15 */ AM33XX_IOPAD(0x9AC, PIN_OUTPUT | MUX_MODE7) /* MCASP0_AHCLKX.GPIO3_21 */ AM33XX_IOPAD(0x9B0, PIN_OUTPUT | MUX_MODE7) /* XDMA_EVENT_INTR0.GPIO0_19 PLC_INTERUPT*/ AM33XX_IOPAD(0x9A0, PIN_OUTPUT | MUX_MODE7) /* MCASP0_ACLKR.GPIO3_18 */ AM33XX_IOPAD(0x9A4, PIN_OUTPUT | MUX_MODE7) /* MCASP0_FSR.GPIO3_19 */ AM33XX_IOPAD(0x998, PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR0.GPIO3_16 */ AM33XX_IOPAD(0x9A8, PIN_OUTPUT | MUX_MODE7) /* MCASP0_AXR1.GPIO3_20 */ AM33XX_IOPAD(0x938, PIN_INPUT | MUX_MODE7) /* MII1_RXD2.GPIO2_19*/ AM33XX_IOPAD(0x888, PIN_OUTPUT | MUX_MODE7) /* GPMC_CSn3.GPIO2_0*/ AM33XX_IOPAD(0x878, PIN_OUTPUT | MUX_MODE7) /* GPMC_ben1.GPIO1_28*/ AM33XX_IOPAD(0x884, PIN_OUTPUT | MUX_MODE7) /* GPMC_CSn2.GPIO1_31*/ AM33XX_IOPAD(0x950, PIN_OUTPUT | MUX_MODE7) /* (A17) spi0_sclk.spi0_sclk */ AM33XX_IOPAD(0x954, PIN_OUTPUT | MUX_MODE7) /* (B17) spi0_d0.spi0_d0 */ AM33XX_IOPAD(0x958, PIN_OUTPUT | MUX_MODE7) /* (B16) spi0_d1.spi0_d1 */ AM33XX_IOPAD(0x95c, PIN_OUTPUT | MUX_MODE7) /* (A16) spi0_cs0.spi0_cs0 */ AM33XX_IOPAD(0x980, PIN_OUTPUT | MUX_MODE7) /* (D16) uart1_rxd.uart1_rxd */ AM33XX_IOPAD(0x984, PIN_OUTPUT | MUX_MODE7) /* (D15) uart1_txd.uart1_txd */ >; }; i2c0_pins_default: i2c0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x98c, PIN_INPUT_PULLUP | MUX_MODE0) /* (C16) I2C0_SCL.I2C0_SCL */ AM33XX_IOPAD(0x988, PIN_INPUT_PULLUP | MUX_MODE0) /* (C17) I2C0_SDA.I2C0_SDA */ >; }; uart0_pins_default: uart0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x970, PIN_INPUT_PULLUP | MUX_MODE0) /* (E15) uart0_rxd.uart0_rxd */ AM33XX_IOPAD(0x974, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (E16) uart0_txd.uart0_txd */ >; }; uart1_pins_default: uart1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x980, PIN_INPUT_PULLUP | MUX_MODE0) /* (D16) uart1_rxd.uart1_rxd */ AM33XX_IOPAD(0x984, PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* (D15) uart1_txd.uart1_txd */ AM33XX_IOPAD(0x978, PIN_INPUT | MUX_MODE0) /* (D18) uart1_ctsn.uart1_ctsn */ AM33XX_IOPAD(0x97c, PIN_OUTPUT | MUX_MODE0) /* (D17) uart1_rtsn.uart1_rtsn */ >; }; uart2_pins_default: uart2_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x92c, PIN_INPUT_PULLUP | MUX_MODE1) /* (K18) gmii1_txclk.uart2_rxd */ AM33XX_IOPAD(0x930, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (L18) gmii1_rxclk.uart2_txd */ >; }; uart3_pins_default: uart3_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x934, PIN_INPUT_PULLUP | MUX_MODE1) /* (L17) gmii1_rxd3.uart3_rxd */ AM33XX_IOPAD(0x964, PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* (C18) eCAP0_in_PWM0_out.uart3_txd */ >; }; uart5_pins_default: uart5_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x908, PIN_INPUT_PULLUP | MUX_MODE3) /* (H16) gmii1_col.uart5_rxd */ AM33XX_IOPAD(0x918, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* (J17) gmii1_rxdv.uart5_txd */ >; }; clkout2_pin: pinmux_clkout2_pin { pinctrl-single,pins = < AM33XX_IOPAD(0x9b4, PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ >; }; #if 1 ecap2_pins: backlight_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x99c, MUX_MODE4) /* mcasp0_ahclkr.ecap2_in_pwm2_out */ >; }; #endif nandflash_pins_default: nandflash_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x81c, PIN_INPUT_PULLUP | MUX_MODE0) /* (T9) gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x818, PIN_INPUT_PULLUP | MUX_MODE0) /* (R9) gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x814, PIN_INPUT_PULLUP | MUX_MODE0) /* (V8) gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x810, PIN_INPUT_PULLUP | MUX_MODE0) /* (U8) gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x80c, PIN_INPUT_PULLUP | MUX_MODE0) /* (T8) gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x808, PIN_INPUT_PULLUP | MUX_MODE0) /* (R8) gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x804, PIN_INPUT_PULLUP | MUX_MODE0) /* (V7) gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x800, PIN_INPUT_PULLUP | MUX_MODE0) /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x870, PIN_INPUT_PULLUP | MUX_MODE0) /* (T17) gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x874, PIN_OUTPUT | MUX_MODE0) /* (U17) gpmc_wpn.gpmc_wpn */ AM33XX_IOPAD(0x890, PIN_OUTPUT | MUX_MODE0) /* (R7) gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x894, PIN_OUTPUT | MUX_MODE0) /* (T7) gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x898, PIN_OUTPUT | MUX_MODE0) /* (U6) gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x89c, PIN_OUTPUT | MUX_MODE0) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x87c, PIN_OUTPUT | MUX_MODE0) /* (V6) gpmc_csn0.gpmc_csn0 */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ nandflash_pins_sleep: nandflash_pins_sleep { pinctrl-single,pins = < AM33XX_IOPAD(0x81c,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (T9) gpmc_ad7.gpmc_ad7 */ AM33XX_IOPAD(0x818,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (R9) gpmc_ad6.gpmc_ad6 */ AM33XX_IOPAD(0x814,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (V8) gpmc_ad5.gpmc_ad5 */ AM33XX_IOPAD(0x810,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (U8) gpmc_ad4.gpmc_ad4 */ AM33XX_IOPAD(0x80c,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (T8) gpmc_ad3.gpmc_ad3 */ AM33XX_IOPAD(0x808,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (R8) gpmc_ad2.gpmc_ad2 */ AM33XX_IOPAD(0x804,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (V7) gpmc_ad1.gpmc_ad1 */ AM33XX_IOPAD(0x800,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (U7) gpmc_ad0.gpmc_ad0 */ AM33XX_IOPAD(0x870,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (T17) gpmc_wait0.gpmc_wait0 */ AM33XX_IOPAD(0x874,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (U17) gpmc_wpn.gpmc_wpn */ AM33XX_IOPAD(0x890,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (R7) gpmc_advn_ale.gpmc_advn_ale */ AM33XX_IOPAD(0x894,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (T7) gpmc_oen_ren.gpmc_oen_ren */ AM33XX_IOPAD(0x898,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (U6) gpmc_wen.gpmc_wen */ AM33XX_IOPAD(0x89c,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (T6) gpmc_be0n_cle.gpmc_be0n_cle */ AM33XX_IOPAD(0x87c,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (V6) gpmc_csn0.gpmc_csn0 */ >; }; cpsw_default: cpsw_default { pinctrl-single,pins = < AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* (H17) mii1_crs.rmii1_crs_dv */ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE0) /* (H18) rmii1_refclk.rmii1_refclk */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE1) /* (L15) gmii1_rxd1.rmii1_rxd1 */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ AM33XX_IOPAD(0x928, PIN_OUTPUT | MUX_MODE1) /* (K17) gmii1_txd0.rmii1_txd0 */ AM33XX_IOPAD(0x924, PIN_OUTPUT | MUX_MODE1) /* (K16) gmii1_txd1.rmii1_txd1 */ AM33XX_IOPAD(0x914, PIN_OUTPUT | MUX_MODE1) /* (J16) gmii1_txen.rmii1_txen */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ cpsw_sleep: cpsw_sleep { pinctrl-single,pins = < AM33XX_IOPAD(0x90c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H17) gmii1_crs.rmii1_crs_dv */ AM33XX_IOPAD(0x914, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (J16) gmii1_txen.rmii1_txen */ AM33XX_IOPAD(0x928, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K17) gmii1_txd0.rmii1_txd0 */ AM33XX_IOPAD(0x924, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (K16) gmii1_txd1.rmii1_txd1 */ AM33XX_IOPAD(0x940, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M16) gmii1_rxd0.rmii1_rxd0 */ AM33XX_IOPAD(0x93c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (L15) gmii1_rxd1.rmii1_rxd1 */ AM33XX_IOPAD(0x944, PIN_INPUT_PULLDOWN | MUX_MODE7) /* (H18) rmii1_refclk.rmii1_refclk */ AM33XX_IOPAD(0x910, PIN_INPUT_PULLDOWN | MUX_MODE7) /* mii1_rxerr.rmii1_rxerr */ >; }; davinci_mdio_default: davinci_mdio_default { pinctrl-single,pins = < AM33XX_IOPAD(0x94c, PIN_OUTPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* (M18) mdio_clk.mdio_clk */ AM33XX_IOPAD(0x948, PIN_INPUT_PULLUP | MUX_MODE0) /* (M17) mdio_data.mdio_data */ >; }; /* Optional sleep pin settings. Must manually enter values in the below skeleton. */ davinci_mdio_sleep: davinci_mdio_sleep { pinctrl-single,pins = < AM33XX_IOPAD(0x94c,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M18) mdio_clk.mdio_clk */ AM33XX_IOPAD(0x948,PIN_INPUT_PULLDOWN | MUX_MODE7) /* (M17) mdio_data.mdio_data */ >; }; mmc1_pins: mmc1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x900, PIN_INPUT_PULLUP | MUX_MODE0) /* (G17) mmc0_clk.mmc0_clk */ AM33XX_IOPAD(0x904, PIN_INPUT_PULLUP | MUX_MODE0) /* (G18) mmc0_cmd.mmc0_cmd */ AM33XX_IOPAD(0x8fc, PIN_INPUT_PULLUP | MUX_MODE0) /* (G16) mmc0_dat0.mmc0_dat0 */ AM33XX_IOPAD(0x8f8, PIN_INPUT_PULLUP | MUX_MODE0) /* (G15) mmc0_dat1.mmc0_dat1 */ AM33XX_IOPAD(0x8f4, PIN_INPUT_PULLUP | MUX_MODE0) /* (F18) mmc0_dat2.mmc0_dat2 */ AM33XX_IOPAD(0x8f0, PIN_INPUT_PULLUP | MUX_MODE0) /* (F17) mmc0_dat3.mmc0_dat3 */ AM33XX_IOPAD(0x960, PIN_INPUT | MUX_MODE7) /* (C15) spi0_cs1.mmc0_sdcd gpio0_6*/ >; }; dcan0_pins_default: dcan0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x920, PIN_INPUT_PULLDOWN | MUX_MODE1) /* (K15) gmii1_txd2.dcan0_rx */ AM33XX_IOPAD(0x91c, PIN_OUTPUT_PULLUP | MUX_MODE1) /* (J18) gmii1_txd3.dcan0_tx */ >; }; dcan1_pins_default: dcan1_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x96c, PIN_INPUT_PULLDOWN | MUX_MODE2) /* (E17) uart0_rtsn.dcan1_rx */ AM33XX_IOPAD(0x968, PIN_OUTPUT_PULLUP | MUX_MODE2) /* (E18) uart0_ctsn.dcan1_tx */ >; }; spi0_pins_default: spi0_pins_default { pinctrl-single,pins = < AM33XX_IOPAD(0x950, PIN_INPUT_PULLUP | MUX_MODE0) /* (A17) spi0_sclk.spi0_sclk */ AM33XX_IOPAD(0x954, PIN_INPUT_PULLUP | MUX_MODE0) /* (B17) spi0_d0.spi0_d0 */ AM33XX_IOPAD(0x958, PIN_OUTPUT_PULLUP | MUX_MODE0) /* (B16) spi0_d1.spi0_d1 */ AM33XX_IOPAD(0x95c, PIN_OUTPUT_PULLUP | MUX_MODE0) /* (A16) spi0_cs0.spi0_cs0 */ >; }; lcd_pins_s0: lcd_pins_s0 { pinctrl-single,pins = < AM33XX_IOPAD(0x820, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x824, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ AM33XX_IOPAD(0x828, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ AM33XX_IOPAD(0x82c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ AM33XX_IOPAD(0x830, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ AM33XX_IOPAD(0x834, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ AM33XX_IOPAD(0x838, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ AM33XX_IOPAD(0x83c, PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ AM33XX_IOPAD(0x8a0, PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a4, PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a8, PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8ac, PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8b0, PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b4, PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b8, PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8bc, PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8c0, PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c4, PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c8, PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8cc, PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8d0, PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d4, PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d8, PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8dc, PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8e0, PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e4, PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e8, PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8ec, PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ >; }; lcd_pins_sleep: lcd_pins_sleep { pinctrl-single,pins = < AM33XX_IOPAD(0x820, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad8.lcd_data23 */ AM33XX_IOPAD(0x824, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad9.lcd_data22 */ AM33XX_IOPAD(0x828, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad10.lcd_data21 */ AM33XX_IOPAD(0x82c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad11.lcd_data20 */ AM33XX_IOPAD(0x830, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad12.lcd_data19 */ AM33XX_IOPAD(0x834, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad13.lcd_data18 */ AM33XX_IOPAD(0x838, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad14.lcd_data17 */ AM33XX_IOPAD(0x83c, PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_ad15.lcd_data16 */ AM33XX_IOPAD(0x8a0, PULL_DISABLE | MUX_MODE7) /* lcd_data0.lcd_data0 */ AM33XX_IOPAD(0x8a4, PULL_DISABLE | MUX_MODE7) /* lcd_data1.lcd_data1 */ AM33XX_IOPAD(0x8a8, PULL_DISABLE | MUX_MODE7) /* lcd_data2.lcd_data2 */ AM33XX_IOPAD(0x8ac, PULL_DISABLE | MUX_MODE7) /* lcd_data3.lcd_data3 */ AM33XX_IOPAD(0x8b0, PULL_DISABLE | MUX_MODE7) /* lcd_data4.lcd_data4 */ AM33XX_IOPAD(0x8b4, PULL_DISABLE | MUX_MODE7) /* lcd_data5.lcd_data5 */ AM33XX_IOPAD(0x8b8, PULL_DISABLE | MUX_MODE7) /* lcd_data6.lcd_data6 */ AM33XX_IOPAD(0x8bc, PULL_DISABLE | MUX_MODE7) /* lcd_data7.lcd_data7 */ AM33XX_IOPAD(0x8c0, PULL_DISABLE | MUX_MODE7) /* lcd_data8.lcd_data8 */ AM33XX_IOPAD(0x8c4, PULL_DISABLE | MUX_MODE7) /* lcd_data9.lcd_data9 */ AM33XX_IOPAD(0x8c8, PULL_DISABLE | MUX_MODE7) /* lcd_data10.lcd_data10 */ AM33XX_IOPAD(0x8cc, PULL_DISABLE | MUX_MODE7) /* lcd_data11.lcd_data11 */ AM33XX_IOPAD(0x8d0, PULL_DISABLE | MUX_MODE7) /* lcd_data12.lcd_data12 */ AM33XX_IOPAD(0x8d4, PULL_DISABLE | MUX_MODE7) /* lcd_data13.lcd_data13 */ AM33XX_IOPAD(0x8d8, PULL_DISABLE | MUX_MODE7) /* lcd_data14.lcd_data14 */ AM33XX_IOPAD(0x8dc, PULL_DISABLE | MUX_MODE7) /* lcd_data15.lcd_data15 */ AM33XX_IOPAD(0x8e0, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_vsync.lcd_vsync */ AM33XX_IOPAD(0x8e4, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_hsync.lcd_hsync */ AM33XX_IOPAD(0x8e8, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_pclk.lcd_pclk */ AM33XX_IOPAD(0x8ec, PIN_INPUT_PULLDOWN | MUX_MODE7) /* lcd_ac_bias_en.lcd_ac_bias_en */ >; }; #if 1 ehrpwm1_pins: ehrpwm1_pins { pinctrl-single,pins = < AM33XX_IOPAD(0x848, PIN_OUTPUT | MUX_MODE6) /* GPMC_A2.ehrpwm1a */ >; }; #endif }; #if 0 &gpio2 { ti,no-reset-on-init; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; }; &gpio2 { pinctrl-names = "default"; pinctrl-0 = <&gpio2_pins_default>; gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; status = "okay"; }; #endif &gpio3 { ti,no-reset-on-init; gpios = <&gpio3 17 GPIO_ACTIVE_LOW>; }; &uart0 { pinctrl-names = "default"; pinctrl-0 = <&uart0_pins_default>; status = "okay"; }; &uart1 { pinctrl-names = "default"; pinctrl-0 = <&uart1_pins_default>; status = "okay"; }; &uart2 { pinctrl-names = "default"; pinctrl-0 = <&uart2_pins_default>; status = "okay"; }; &uart3 { pinctrl-names = "default"; pinctrl-0 = <&uart3_pins_default>; status = "okay"; }; &uart5 { pinctrl-names = "default"; pinctrl-0 = <&uart5_pins_default>; status = "okay"; }; &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0_pins_default>; status = "okay"; clock-frequency = <400000>; tps: tps@2d { reg = <0x2d>; }; }; &usb { status = "okay"; }; &usb_ctrl_mod { status = "okay"; }; &usb0_phy { status = "okay"; }; &usb1_phy { status = "okay"; }; &usb0 { status = "okay"; }; &usb1 { status = "okay"; dr_mode = "host"; }; &cppi41dma { status = "okay"; }; &elm { status = "okay"; }; #if 1 &epwmss2 { status = "okay"; ecap2: ecap@48304100 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ecap2_pins>; }; }; #endif &gpmc { status = "okay"; pinctrl-names = "default", "sleep"; pinctrl-0 = <&nandflash_pins_default>; pinctrl-1 = <&nandflash_pins_sleep>; ranges = <0 0 0x08000000 0x20000000>; /* CS0: NAND */ /* ranges = <0 0 0x08000000 0x80000000>; +++ Seamus,NAND,20190318 ---*/ nand@0,0 { compatible = "ti,omap2-nand"; reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ interrupt-parent = <&gpmc>; interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */ <1 IRQ_TYPE_NONE>; /* termcount */ rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */ ti,nand-ecc-opt = "bch8"; ti,elm-id = <&elm>; nand-bus-width = <8>; gpmc,device-width = <1>; gpmc,sync-clk-ps = <0>; gpmc,cs-on-ns = <0>; gpmc,cs-rd-off-ns = <44>; gpmc,cs-wr-off-ns = <44>; gpmc,adv-on-ns = <6>; gpmc,adv-rd-off-ns = <34>; gpmc,adv-wr-off-ns = <44>; gpmc,we-on-ns = <0>; gpmc,we-off-ns = <40>; gpmc,oe-on-ns = <0>; gpmc,oe-off-ns = <54>; gpmc,access-ns = <64>; gpmc,rd-cycle-ns = <82>; gpmc,wr-cycle-ns = <82>; gpmc,wait-on-read = "true"; gpmc,wait-on-write = "true"; gpmc,bus-turnaround-ns = <0>; gpmc,cycle2cycle-delay-ns = <0>; gpmc,clk-activation-ns = <0>; gpmc,wait-monitoring-ns = <0>; gpmc,wr-access-ns = <40>; gpmc,wr-data-mux-bus-ns = <0>; /* MTD partition table */ /* All SPL-* partitions are sized to minimal length * which can be independently programmable. For * NAND flash this is equal to size of erase-block */ #address-cells = <1>; #size-cells = <1>; partition@0 { label = "NAND.SPL"; reg = <0x00000000 0x00080000>; /* 512KB */ }; partition@1 { label = "NAND.SPL.backup1"; reg = <0x00080000 0x00080000>; /* 512KB */ }; partition@2 { label = "NAND.SPL.backup2"; reg = <0x00100000 0x00080000>; /* 512KB */ }; partition@3 { label = "NAND.SPL.backup3"; reg = <0x00180000 0x00080000>; /* 512KB */ }; partition@4 { label = "NAND.kernel-fdt"; reg = <0x00200000 0x00080000>; /* 512KB */ }; partition@5 { label = "NAND.u-boot"; reg = <0x00280000 0x00100000>; /* 1MB */ }; partition@6 { label = "NAND.u-boot-env"; /* 512KB */ reg = <0x00380000 0x00080000>; }; partition@7 { label = "Primary kernel"; reg = <0x00400000 0x00A00000>; }; partition@8 { label = "Secondary kernel"; reg = <0x00E00000 0x00A00000>; }; partition@9 { label = "Primary rootfs"; reg = <0x01800000 0x01800000>; }; partition@10 { label = "Secondary rootfs"; reg = <0x03000000 0x01800000>; }; partition@11 { label = "Primary user configuration"; reg = <0x04800000 0x00600000>; }; partition@12 { label = "Secondary user configuration"; reg = <0x04E00000 0x00600000>; }; partition@13 { label = "Factory default configuration"; reg = <0x05400000 0x00600000>; }; partition@14 { label = "Storage"; reg = <0x05A00000 0x7A600000>; }; }; }; #include "tps65910.dtsi" #if 0 &mcasp1 { #sound-dai-cells = <0>; pinctrl-names = "default", "sleep"; pinctrl-0 = <&mcasp1_pins>; pinctrl-1 = <&mcasp1_pins_sleep>; status = "okay"; op-mode = <0>; /* MCASP_IIS_MODE */ tdm-slots = <2>; /* 4 serializers */ serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 0 0 1 2 >; tx-num-evt = <32>; rx-num-evt = <32>; }; #endif &tps { vcc1-supply = <&vbat>; vcc2-supply = <&vbat>; vcc3-supply = <&vbat>; vcc4-supply = <&vbat>; vcc5-supply = <&vbat>; vcc6-supply = <&vbat>; vcc7-supply = <&vbat>; vccio-supply = <&vbat>; regulators { vrtc_reg: regulator@0 { regulator-always-on; }; vio_reg: regulator@1 { regulator-always-on; }; vdd1_reg: regulator@2 { /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */ regulator-name = "vdd_mpu"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1378000>; regulator-boot-on; regulator-always-on; }; vdd2_reg: regulator@3 { /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ regulator-name = "vdd_core"; regulator-min-microvolt = <912500>; regulator-max-microvolt = <1150000>; regulator-boot-on; regulator-always-on; }; vdd3_reg: regulator@4 { regulator-always-on; }; vdig1_reg: regulator@5 { regulator-always-on; }; vdig2_reg: regulator@6 { regulator-always-on; }; vpll_reg: regulator@7 { regulator-always-on; }; vdac_reg: regulator@8 { regulator-always-on; }; vaux1_reg: regulator@9 { regulator-always-on; }; vaux2_reg: regulator@10 { regulator-always-on; }; vaux33_reg: regulator@11 { regulator-always-on; }; vmmc_reg: regulator@12 { regulator-min-microvolt = <1800000>; regulator-max-microvolt = <3300000>; regulator-always-on; }; }; }; &mac { pinctrl-names = "default", "sleep"; pinctrl-0 = <&cpsw_default>; pinctrl-1 = <&cpsw_sleep>; status = "okay"; }; &davinci_mdio { pinctrl-names = "default", "sleep"; pinctrl-0 = <&davinci_mdio_default>; pinctrl-1 = <&davinci_mdio_sleep>; status = "okay"; }; &cpsw_emac0 { phy-mode = "rmii"; fixed-link { speed = <100>; full-duplex; }; }; &phy_sel { rmii-clock-ext = <1>; }; &tscadc { status = "okay"; adc { ti,adc-channels = <0>; ti,chan-step-opendelay = <0x0>; ti,chan-step-sampledelay = <0x1>; ti,chan-step-avg = <0>; }; }; /* Miscro SD */ &mmc1 { status = "okay"; vmmc-supply = <&vmmc_reg>; bus-width = <4>; pinctrl-names = "default"; pinctrl-0 = <&mmc1_pins>; cd-gpios = <&gpio0 6 GPIO_ACTIVE_LOW>; }; &sham { status = "okay"; }; &aes { status = "okay"; }; &wkup_m3_ipc { ti,scale-data-fw = "am335x-evm-scale-data.bin"; }; &dcan0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcan0_pins_default>; }; &dcan1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&dcan1_pins_default>; }; #if 1 &epwmss1 { status = "okay"; }; &ehrpwm1 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&ehrpwm1_pins>; }; #endif /* The QCA7000 acts as a SPI slave and uses Mode 3: CPOL=1, CPHA=1. SPI data width is 8 bit. The SPI CLK period should not be less than 83.3 ns The SPI should be used in burst mode, meaning that the chip select is held low during a complete SPI message. Note: The SPI lines between Host CPU and QCA7000 should be kept as short as possible. */ #if 0 /* Green PHY (QCA7000) */ &spi0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&spi0_pins_default>; qca7000: ethernet@0 { reg = <0x0>; compatible = "qca,qca7000"; interrupt-parent = <&gpio0>; interrupts = <19 IRQ_TYPE_EDGE_RISING>; spi-cpha; spi-cpol; spi-max-frequency = <10000000>; status = "okay"; }; }; #endif &lcdc { status = "okay"; blue-and-red-wiring = "crossed"; }; #if 0 &rtc { clocks = <&clk_32768_ck>, <&clkdiv32k_ick>; clock-names = "ext-clk", "int-clk"; }; &pruss_soc_bus { status = "okay"; pruss: pruss@0 { status = "okay"; }; }; &sgx { status = "okay"; }; #endif