/*
 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#include "dra7-evm-lcd-lg.dts"


#define DISABLE_PRCM(label) &label { ti,no-idle; ti,no-reset-on-init; }
#define DISABLE_COMPLETE(label) &label { status = "disabled"; ti,no-idle; ti,no-reset-on-init; }
#define LATE_ATTACH(label) &label { ti,late-attach; ti,no-idle; ti,no-reset-on-init; }


/* modules used by BIOS, disable from Linux */
//DISABLE_COMPLETE(vip1);
//DISABLE_COMPLETE(vip2);
//DISABLE_COMPLETE(vip3);
//DISABLE_COMPLETE(i2c2);
DISABLE_COMPLETE(wdt2);
//DISABLE_COMPLETE(vpe);
DISABLE_COMPLETE(ocmcram1);
DISABLE_COMPLETE(hdmi);
DISABLE_COMPLETE(hdmi0);

/* modules shared between BIOS and Linux, Do not reset or cutoff clks */
DISABLE_PRCM(gpio1);
DISABLE_PRCM(gpio2);
DISABLE_PRCM(gpio4);
DISABLE_PRCM(gpio6);


/*
 * Restrict the linux used EDMA requests to only 32
 * Last 32 requests lines would be routed by the edma-xbar
 * to perform DMA for DSPs and IPUs
 */
&edma {
	dma-requests = <32>;
};


/*
 * Memory reserved for IOMMU table carveout 0xbfc00000 for length 0x100000
 * Page Table Address for IPU1   0xbfc00000
 * Page Table Address for IPU2   0xbfc08000
 * Page Table Address for DSP1   0xbfc10000
 * Page Table Address for DSP2   0xbfc18000
 */
&reserved_mem {

	vsdk_sr1_mem: vsdk_sr1_mem@84000000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0x84000000 0x0 0x15000000>;
		status = "okay";
	};

	vsdk_sr0_mem: vsdk_sr0_mem@A0000000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0xA0000000 0x0 0x1000000>;
		status = "okay";
	};

	vsdk_eve_mem: vsdk_eve_mem@A5000000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0xA5000000 0x0 0x4000000>;
		status = "okay";
	};
	
	vsdk_sr3_mem: vsdk_eve_mem@B3000000 {
		compatible = "shared-dma-pool";
		reg = <0x0 0xB3000000 0x0 0xD000000>;
		status = "okay";
	};
};

/* Uncomment below block to enable late attach for IPU2 */
LATE_ATTACH(ipu2);
LATE_ATTACH(timer3);
LATE_ATTACH(timer4);
LATE_ATTACH(timer9);
LATE_ATTACH(mmu_ipu2);

/* Uncomment below block to enable late attach for IPU1 */
LATE_ATTACH(ipu1);
LATE_ATTACH(timer11);
LATE_ATTACH(timer7);
LATE_ATTACH(timer8);
LATE_ATTACH(mmu_ipu1);

/* Uncomment below block to enable late attach for DSP1 */
LATE_ATTACH(dsp1);
LATE_ATTACH(timer5);
LATE_ATTACH(timer10);
LATE_ATTACH(mmu0_dsp1);
LATE_ATTACH(mmu1_dsp1);

/* Uncomment below block to enable late attach for DSP2 */
LATE_ATTACH(dsp2);
LATE_ATTACH(timer6);
LATE_ATTACH(mmu0_dsp2);
LATE_ATTACH(mmu1_dsp2);


LATE_ATTACH(timer13);
LATE_ATTACH(timer14);
LATE_ATTACH(mailbox5);
LATE_ATTACH(mailbox6);
LATE_ATTACH(mailbox7);