/*--------------------------------------------------------------*/
/* StartUp()                                                    */
/*--------------------------------------------------------------*/
StartUp()
{
}

/*--------------------------------------------------------------*/
/* OnTargetConnect()                                            */
/*--------------------------------------------------------------*/
OnTargetConnect()
{
//    init_emif();
}

/*--------------------------------------------------------------*/
/* OnReset()                                                    */
/*--------------------------------------------------------------*/
OnReset( int nErrorCode )
{
    init_emif();
}

/*--------------------------------------------------------------*/
/* OnPreFileLoaded()                                            */
/*--------------------------------------------------------------*/
OnPreFileLoaded()
{
//   init_emif();
}

/*--------------------------------------------------------------*/
/* OnRestart()                                                  */
/*--------------------------------------------------------------*/
OnRestart(int nErrorCode )
{
//    init_emif();
}

/*--------------------------------------------------------------*/
/* init_emif()                                                  */
/*--------------------------------------------------------------*/
init_emif()
{
	int i;

    #define EMIF_AWCCR       0xf0000004     // async wait cycle config
    #define EMIF_SDCR        0xf0000008     // SDRAM config reg
    #define EMIF_SDRCR       0xf000000c     // SDRAM refresh control
    #define EMIF_A1CR        0xf0000010     // asynchronous 1 config
    #define EMIF_SDTIMR      0xf0000020     // SDRAM timing register
    #define EMIF_SDSRETR     0xf000003c     // SDRAM self refresh exit timing register
    #define EMIF_EIRR        0xf0000040     // interrupt raw
    #define EMIF_EIMR        0xf0000044     // interrupt mask reg
    #define EMIF_EIMSR       0xf0000048     // interrupt mask set
    #define EMIF_EIMCR       0xf000004c     // interrupt mask clear reg

               
    *(char *)(EMIF_SDCR+3) = 0x80;          // enter self-refresh mode

    init_pll();                             // set EMIF-clock
    
  /* EMIF setup */
	*(int *)EMIF_AWCCR =  ( 0 << 28)	// WP0      : Insert wait cycle if AWAIT is low
						| (16 <<  0);	// MEMC     : Max extended wait cycles (max = 16*(MEWC+1))

	*(int *)EMIF_SDTIMR = ( 6 << 27)	// T_RFC : Auto refresh period (66ns)
 						| ( 1 << 24)	// T_RP  : Precharge command period (20 ns) 
						| ( 1 << 20)	// T_RCD : Active to read or write delay (20 ns)
						| ( 1 << 16)	// T_WR  : Write recovery time (1 clk + 7.5 ns)
						| ( 4 << 12)	// T_RAS : Active to precharge command (44 ns) 
						| ( 6 <<  8)	// T_RC  : Active to active command period (66 ns)
						| ( 1 <<  4);	// T_RRD : Active bank a to active bank b command (15 ns)

//	*(int *)EMIF_SDTIMR = ( 4 << 27)	// T_RFC : Auto refresh period (66ns)
// 						| ( 1 << 24)	// T_RP  : Precharge command period (20 ns) 
//						| ( 1 << 20)	// T_RCD : Active to read or write delay (20 ns)
//						| ( 1 << 16)	// T_WR  : Write recovery time (1 clk + 7.5 ns)
//						| ( 2 << 12)	// T_RAS : Active to precharge command (44 ns) 
//						| ( 2 <<  8)	// T_RC  : Active to active command period (66 ns)
//						| ( 1 <<  4);	// T_RRD : Active bank a to active bank b command (15 ns)

	*(int *)EMIF_SDSRETR  = 6;	// T_RFC : Auto refresh period (66ns)

	*(int *)EMIF_SDRCR    = 0x000004E2;

	*(int *)EMIF_SDCR  =   ( 0 << 31)	// SR          : To avoid self refresh state
						 | ( 0 << 14)	// NM          : Not narrow (32-bit)
						 | ( 2 <<  9)	// CL          : 2 clock 
						 | ( 1 <<  8)	// BIT11_9LOCK : To allow the CL field to be written (legacy) 
						 | ( 2 <<  4)	// IBANK       : 4 internal SDRAM banks
						 | ( 1 <<  0);	// PAGESIZE    : 256 word pages

	*(int *)EMIF_A1CR =   ( 0 << 31)	// SS       : Select WE mode
					    | ( 0 << 30)	// EW       : Enable extended wait mode
						| ( 4 << 26)	// W_SETUP  :  10 ns @ 100 MHz
						| ( 15 << 20)	// W_STROBE :  50 ns @ 100 MHz
						| ( 4 << 17)	// W_HOLD   :  40 ns @ 100 MHz
						| ( 4 << 13)	// R_SETUP  :  10 ns @ 100 MHz
						| ( 15 <<  7)	// R_STROBE :  50 ns @ 100 MHz
						| ( 4 <<  4)	// R_HOLD   :  40 ns @ 100 MHz
						| ( 2 <<  2)	// TA       :  10 ns @ 100 MHz
						| ( 2 <<  0);	// ASIZE    :  16-bit data bus

//	*(int *)EMIF_A1CR =   ( 0 << 31)	// SS       : Select WE mode
//					    | ( 0 << 30)	// EW       : Enable extended wait mode
//						| ( 0 << 26)	// W_SETUP  :  10 ns @ 100 MHz
//						| ( 1 << 20)	// W_STROBE :  50 ns @ 100 MHz
//						| ( 0 << 17)	// W_HOLD   :  40 ns @ 100 MHz
//						| ( 0 << 13)	// R_SETUP  :  10 ns @ 100 MHz
//						| ( 2 <<  7)	// R_STROBE :  50 ns @ 100 MHz
//						| ( 0 <<  4)	// R_HOLD   :  40 ns @ 100 MHz
//						| ( 0 <<  2)	// TA       :  10 ns @ 100 MHz
//						| ( 1 <<  0);	// ASIZE    :  16-bit data bus

	i = *(int *)(0x80000000);

	*(int *)EMIF_SDRCR = 0x0000061A;
    GEL_TextOut("GEL Init EMIF Complete.\n");
}

/*--------------------------------------------------------------*/
/* init_pll()                                                   */
/*--------------------------------------------------------------*/
init_pll()
{

	#define PLL_PID           0x41000000
	#define PLL_CFGBRIDGE     0x40000024
	#define PLL_CSR           0x41000100
	#define PLL_M             0x41000110
	#define PLL_DIV0          0x41000114
	#define PLL_DIV1          0x41000118
	#define PLL_DIV2          0x4100011C
	#define PLL_DIV3          0x41000120
	#define PLL_CMD           0x41000138
	#define PLL_STAT          0x4100013c
	#define ALN_CTL           0x41000140
	#define CKEN              0x41000148
	#define CKSTAT            0x4100014c
	#define SYSTAT            0x41000150

	/* FOR PLLCSR */
	#define PLLENABLE         0x01
	#define PLLDISABLE        0x00
	#define PLLPWRDN          0x02
	#define PLLPWRUP          0x00
	#define PLLOSCPWRDN       0x04
	#define PLLOSCPWRUP       0x00
	#define PLLRESET          0x08
	#define PLLRESETRELEASE   0x00
	#define PLLSTABLE         0x40
	#define PLLUNSTABLE       0x00

	/* FOR PLLCMD */
	#define PLLGOCLR          0x0000
	#define PLLGOSET          0x0001

	/* FOR PLLSTAT */
	#define PLLGODONE         0x0000
	#define PLLGOWAIT         0x0001

	/* FOR ALNCTL */
	#define PLLALN1           0x0001
	#define PLLALN2           0x0002
	#define PLLALN3           0x0004

	/* FOR PLLDIV0,1,2,3*/
	#define DIVENABLED        0x8000
	#define DIV1              0x0000
	#define DIV2              0x0001 
	#define DIV3              0x0002
	#define DIV4              0x0003
	#define DIV5              0x0004
	#define DIV6              0x0005

	int i;

	/* 1. In PLLCSR, write PLLEN = 0 (bypass mode) */
	*(int *)PLL_CSR = PLLDISABLE;

	/* 2. Wait 4 cycles of the slowest of PLLOUT or reference clock source (CLKIN or OSCIN) */
	for(i=0;i<1000;i++);

	/* 3. In PLLCSR, write PLLRST = 1 (PLL is reset) */
	*(int *)PLL_CSR = PLLDISABLE | PLLRESET;
	for(i=0;i<1000;i++);

	/* 4. If necessary, program PLLDIV0 and PLLM */
	/* Clock input is xx.000 MHz                              */
	/* DIV0 - Before PLL(set to/1)                            */
	*(int *)PLL_DIV0 = DIVENABLED | DIV1;

	*(int *)PLL_M       = 10;

	for(i=0;i<1000;i++);

	/* 5. If necessary, program PLLDIV1-n. Note that you must apply the GO operation to 
		change these dividers to new ratios. */
	/* DIV1 - After PLL- SYSCLK1 DSP Core                     */
	/* DIV2 - After PLL- SYSCLK2 PERIPHS (Always twice DIV2)  */
	/* DIV3 - After PLL- SYSCLK3 EMIF CLOCK                   */
	*(int *)PLL_DIV1 = DIVENABLED | DIV1;
	for(i=0;i<1000;i++);                       
	*(int *)PLL_DIV2 = DIVENABLED | DIV2;
	for(i=0;i<1000;i++);                       
	*(int *)PLL_DIV3 = DIVENABLED | DIV3;
	for(i=0;i<1000;i++);                       

	/* Enable PLL Align control. */
	*(int *)ALN_CTL = PLLALN1 | PLLALN2 | PLLALN3;
	*(int *)PLL_CMD = PLLGOSET;

	while (*(int *)PLL_STAT == PLLGOWAIT);

	*(int *)PLL_CMD = PLLGOCLR;

	/* 6. Wait for PLL to properly reset */
	/* Reset wait time is 125 ns */
	for(i=0;i<1000;i++);

	/* 7. In PLLCSR, write PLLRST = 0 to bring PLL out of reset */
	*(int *)PLL_CSR = PLLDISABLE | PLLRESETRELEASE;

	/* 8. Wait for PLL to lock */
	/* Lock time after changing D0, PLLM, or input clock is 187.5 us */
	for(i=0;i<65535;i++);

	/* 9. In PLLCSR, write PLLEN = 1 to enable PLL mode *. */
	*(int *)PLL_CSR = PLLENABLE | PLLRESETRELEASE;

	/* 10. Bridge reset */
	*(int *)PLL_CFGBRIDGE = 1;		/* Assert reset */
	for(i=0;i<1000;i++);			
	*(int *)PLL_CFGBRIDGE = 0;		/* De-assert reset */
	for(i=0;i<1000;i++);			
    GEL_TextOut("GEL Init PLL Complete.\n");
}

menuitem "Funcs";

hotmenu InitPll()
{
	init_pll();
}

hotmenu InitEmif()
{
	init_emif();
}

hotmenu InitGPIOs()
{
	int *p = (int *)0x4300000c;

	*p = 1 << 9;

	*(int *)0x43000010 = (1 << 21) + (1 << 20);
	*(int *)0x43000014 = (1 << 21) + (1 << 20);
}

hotmenu ToglHd2021()
{
	*(int *)0x43000014 ^= (1 << 21) + (1 << 20);
}