C66xx_24: GEL Output: ****************************************************************************************************************
C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: DDR SDRAM Configuration Register (SDCFG)
C66xx_24: GEL Output: DDR3AEMIF_SDCFG:			0x62004662 (Address: 0x21010008)
C66xx_24: GEL Output: 	SDRAM Type[31:29]:   		DDR3 (3)
C66xx_24: GEL Output: 	SDRAM Drive[27:25]:  		RZQ/4 (1)
C66xx_24: GEL Output: 	Dynamic ODT[23:22]:  		OFF (0)
C66xx_24: GEL Output: 	CAS Write Latency[16:14]:	6 (1)
C66xx_24: GEL Output: 	Data Bus Width[13:12]: 		64-bit (0)
C66xx_24: GEL Output: 	CAS Latency[11:8]:		7 (6)
C66xx_24: GEL Output: 	Banks per SDRAM[6:5]: 		8 (3)
C66xx_24: GEL Output: 	Chip Select Setup[3]: 		DCE0# (0)
C66xx_24: GEL Output: 	Page Size[1:0]:    		1024 word page (2)
C66xx_24: GEL Output: ********************************************************

C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: SDRAM Refresh Control Register (SDRFC)
C66xx_24: GEL Output: DDR3AEMIF_SDRFC:			0x00000C34 (Address: 0x21010010)
C66xx_24: GEL Output: 	INITREF_DIS[31]:		Normal operation
C66xx_24: GEL Output: 	REFRESH_RATE[15:0]:		3124 (REFRESH_RATE = Refresh period * DDR3 clock frequency.)
C66xx_24: GEL Output: ********************************************************

C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: SDRAM Timing 1 Register (SDTIM1)
C66xx_24: GEL Output: DDR3AEMIF_SDTIM1:			0x0E405C43 (Address: 0x21010018)
C66xx_24: GEL Output: 	T_WR[29:25]:			7 cycles (+1)
C66xx_24: GEL Output: 	T_RAS[24:18]:			16 cycles (+1)
C66xx_24: GEL Output: 	T_RC[17:10]:			23 cycles (+1)
C66xx_24: GEL Output: 	T_RRD[9:4]:			4 cycles (+1)
C66xx_24: GEL Output: 	T_WTR[3:0]:			3 cycles (+1)
C66xx_24: GEL Output: ********************************************************

C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: SDRAM Timing 2 Register (SDTIM2)
C66xx_24: GEL Output: DDR3AEMIF_SDTIM2:			0x00001CC6 (Address: 0x2101001C)
C66xx_24: GEL Output: 	T_RTW[12:10]:			7 cycles (+1)
C66xx_24: GEL Output: 	T_RP[9:5]:			6 cycles (+1)
C66xx_24: GEL Output: 	T_RCD[4:0]:			6 cycles (+1)
C66xx_24: GEL Output: ********************************************************

C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: SDRAM Timing 3 Register (SDTIM3)
C66xx_24: GEL Output: DDR3AEMIF_SDTIM3:			0x2219FF32 (Address: 0x21010020)
C66xx_24: GEL Output: 	T_XP[31:28]:			2 cycles (+1)
C66xx_24: GEL Output: 	T_XSNR[27:18]:			134 cycles (+1)
C66xx_24: GEL Output: 	T_XSRD[17:8]:			511 cycles (+1)
C66xx_24: GEL Output: 	T_RTP[7:4]:			3 cycles (+1)
C66xx_24: GEL Output: 	T_CKE[3:0]:			2 cycles (+1)
C66xx_24: GEL Output: ********************************************************

C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: SDRAM Timing 4 Register (SDTIM4)
C66xx_24: GEL Output: 	DDR3AEMIF_SDTIM4:		0x533F081F (Address: 0x21010028)
C66xx_24: GEL Output: 	T_CSTA[31:28]:			2 cycles (+1)
C66xx_24: GEL Output: 	T_CKESR[27:24]:			2 cycles (+1)
C66xx_24: GEL Output: 	ZQ_ZQCS[23:16]:			25 cycles (+1)
C66xx_24: GEL Output: 	T_RFC[13:4]:			1011 cycles (+1)
C66xx_24: GEL Output: 	T_RAS_MAX[3:0]:(should be 0xF)	2 cycles
C66xx_24: GEL Output: ********************************************************

C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: SDRAM Output Impedance Calibration Configuration Register (ZQCFG)
C66xx_24: GEL Output: 	DDR3AEMIF_ZQCFG:		0x70073200 (Address: 0x210100C8)
C66xx_24: GEL Output: 	ZQ_CS1EN[31]:			ZQ calibration for Rank 2 is Disabled (0)
C66xx_24: GEL Output: 	ZQ_CS0EN[31]:			ZQ calibration for Rank 1 is Enabled (1)
C66xx_24: GEL Output: 	ZQ_DUALCALEN[29]:		Dual ZQ calibration is Enabled (1)
C66xx_24: GEL Output: 	ZQ_SFEXITEN[28]:		ZQ calibration on self-refresh, Active power-down and precharge power-down exit is Enabled (1)
C66xx_24: GEL Output: 	ZQ_ZQCL_MULT[18:16]:		7 cycles
C66xx_24: GEL Output: 	ZQ_REFINTERVAL[15:0]:		Refresh periods between ZQCS commands is 12800 (+1)
C66xx_24: GEL Output: ********************************************************
C66xx_24: GEL Output: ****************************************************************************************************************