arm_A15_0: GEL Output: DDR3B PLL Setup ... arm_A15_0: GEL Output: Lammar DDR3 PLL Setup complete, DDR3B clock now running at 666MHz. arm_A15_0: GEL Output: DDR3B_DCR = 0x0000040B arm_A15_0: GEL Output: DDR3B_DATX8_8 Front = 0xB000000F arm_A15_0: GEL Output: DDR3B_DATX8_8 rear = 0xB000000E arm_A15_0: GEL Output: DDR3B_PGSR0 = 0xB1C001FF arm_A15_0: GEL Output: DDR3B_PGSR1 = 0x00000000 arm_A15_0: GEL Output: DDR3B 1600 initialization complete arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: DDR PLL Registers: arm_A15_0: GEL Output: DDR3B_PLL_CTL0 register: 0x092804C0 (0x02620368) arm_A15_0: GEL Output: PLLD[5:0]: 0 (Pre-Divide value of 1) arm_A15_0: GEL Output: PLLM[18:6]: 19 (Multiplier value of 20) arm_A15_0: GEL Output: CLKOD[22:19]: 5 (Output Divide value of 6) arm_A15_0: GEL Output: BYPASS[23]: 0 arm_A15_0: GEL Output: BWADJ-lower[31:24]: 9 arm_A15_0: GEL Output: DDR3B_PLL_CTL1 register: 0x00000040 arm_A15_0: GEL Output: PLLRESET[14]: Reset ** DEASSERTED ** to PLL arm_A15_0: GEL Output: ENSAT[6]: ENSAT is SET - (GOOD) arm_A15_0: GEL Output: BWADJ-upper[3:0]: 0 arm_A15_0: GEL Output: BWADJ[11:0] (combined): 9 arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: DDR SDRAM Configuration Register (SDCFG) arm_A15_0: GEL Output: DDR3BEMIF_SDCFG: 0x6200CE62 (Address: 0x21020008) arm_A15_0: GEL Output: SDRAM Type[31:29]: DDR3 (3) arm_A15_0: GEL Output: SDRAM Drive[27:25]: RZQ/4 (1) arm_A15_0: GEL Output: Dynamic ODT[23:22]: OFF (0) arm_A15_0: GEL Output: CAS Write Latency[16:14]: 8 (3) arm_A15_0: GEL Output: Data Bus Width[13:12]: 64-bit (0) arm_A15_0: GEL Output: CAS Latency[11:8]: 11 (14) arm_A15_0: GEL Output: Banks per SDRAM[6:5]: 8 (3) arm_A15_0: GEL Output: Chip Select Setup[3]: DCE0# (0) arm_A15_0: GEL Output: Page Size[1:0]: 1024 word page (2) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: SDRAM Refresh Control Register (SDRFC) arm_A15_0: GEL Output: DDR3BEMIF_SDRFC: 0x00001869 (Address: 0x21020010) arm_A15_0: GEL Output: INITREF_DIS[31]: Normal operation arm_A15_0: GEL Output: REFRESH_RATE[15:0]: 6249 (REFRESH_RATE = Refresh period * DDR3 clock frequency.) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: SDRAM Timing 1 Register (SDTIM1) arm_A15_0: GEL Output: DDR3BEMIF_SDTIM1: 0x166C9855 (Address: 0x21020018) arm_A15_0: GEL Output: T_WR[29:25]: 11 cycles (+1) arm_A15_0: GEL Output: T_RAS[24:18]: 27 cycles (+1) arm_A15_0: GEL Output: T_RC[17:10]: 38 cycles (+1) arm_A15_0: GEL Output: T_RRD[9:4]: 5 cycles (+1) arm_A15_0: GEL Output: T_WTR[3:0]: 5 cycles (+1) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: SDRAM Timing 2 Register (SDTIM2) arm_A15_0: GEL Output: DDR3BEMIF_SDTIM2: 0x00001D4A (Address: 0x2102001C) arm_A15_0: GEL Output: T_RTW[12:10]: 7 cycles (+1) arm_A15_0: GEL Output: T_RP[9:5]: 10 cycles (+1) arm_A15_0: GEL Output: T_RCD[4:0]: 10 cycles (+1) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: SDRAM Timing 3 Register (SDTIM3) arm_A15_0: GEL Output: DDR3BEMIF_SDTIM3: 0x35DFF53A (Address: 0x21020020) arm_A15_0: GEL Output: T_XP[31:28]: 3 cycles (+1) arm_A15_0: GEL Output: T_XSNR[27:18]: 375 cycles (+1) arm_A15_0: GEL Output: T_XSRD[17:8]: 1013 cycles (+1) arm_A15_0: GEL Output: T_RTP[7:4]: 3 cycles (+1) arm_A15_0: GEL Output: T_CKE[3:0]: 10 cycles (+1) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: SDRAM Timing 4 Register (SDTIM4) arm_A15_0: GEL Output: DDR3BEMIF_SDTIM4: 0x543F0CFF (Address: 0x21020028) arm_A15_0: GEL Output: T_CSTA[31:28]: 3 cycles (+1) arm_A15_0: GEL Output: T_CKESR[27:24]: 5 cycles (+1) arm_A15_0: GEL Output: ZQ_ZQCS[23:16]: 223 cycles (+1) arm_A15_0: GEL Output: T_RFC[13:4]: 851 cycles (+1) arm_A15_0: GEL Output: T_RAS_MAX[3:0]:(should be 0xF) 10 cycles arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: SDRAM Output Impedance Calibration Configuration Register (ZQCFG) arm_A15_0: GEL Output: DDR3BEMIF_ZQCFG: 0x70073200 (Address: 0x210200C8) arm_A15_0: GEL Output: ZQ_CS1EN[31]: ZQ calibration for Rank 2 is Disabled (0) arm_A15_0: GEL Output: ZQ_CS0EN[31]: ZQ calibration for Rank 1 is Enabled (1) arm_A15_0: GEL Output: ZQ_DUALCALEN[29]: Dual ZQ calibration is Enabled (1) arm_A15_0: GEL Output: ZQ_SFEXITEN[28]: ZQ calibration on self-refresh, Active power-down and precharge power-down exit is Enabled (1) arm_A15_0: GEL Output: ZQ_ZQCL_MULT[18:16]: 7 cycles arm_A15_0: GEL Output: ZQ_REFINTERVAL[15:0]: Refresh periods between ZQCS commands is 12800 (+1) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: PLL Control Register (PLLCR) arm_A15_0: GEL Output: DDR3B_PLLCR: 0x000DE000 (Address: 0x02328018) arm_A15_0: GEL Output: FRQSEL[19:18]: PLL Reference clock ranges from 166MHz to 275MHz (3) arm_A15_0: GEL Output: Note: PLL Reference Clock should be 1/4 of DDR data rate. (i.e. 400MHz -> 1600MTs) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: DRAM Timing Parameters Register 0 (DTPR0) arm_A15_0: GEL Output: DDR3B_DTPR0: 0x8558AA75 (Address: 0x02328048) arm_A15_0: GEL Output: tRFC[31:26]: Activate to Activate command delay (same bank) is 33 cycles arm_A15_0: GEL Output: tRRD[25:22]: Activate to Activate command delay (diff banks) is 5 cycles arm_A15_0: GEL Output: tRAS[21:16]: Activate to Precharge command delay is 24 cycles arm_A15_0: GEL Output: tRCD[15:12]: Activate to Read/Write (on activated row) command delay is 10 cycles arm_A15_0: GEL Output: tRP[11:8]: Precharge command period is 10 cycles arm_A15_0: GEL Output: tWTR[7:4]: Internal write to read command delay is 7 cycles arm_A15_0: GEL Output: tRTP[3:0]: Internal read to precharge command delay is 5 cycles arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: DRAM Timing Parameters Register 1 (DTPR1) arm_A15_0: GEL Output: DDR3B_DTPR1: 0x32857370 (Address: 0x0232804C) arm_A15_0: GEL Output: tWLO[29:26]: Write leveling output delay is 12 cycles arm_A15_0: GEL Output: tWLMRD[25:20]: Min delay from write leveling mode to first DQS edge is 40 cycles arm_A15_0: GEL Output: tRFC[19:11]: Refresh to Refresh command delay is 174 cycles arm_A15_0: GEL Output: tFAW[10:5]: 4-bank activate period is 27 cycles arm_A15_0: GEL Output: tMOD[4:2]: Load mode update delay is Reserved Value cycles (16) arm_A15_0: GEL Output: tMRD[1:0]: Load mode cycle time is 0 cycles arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: DRAM Timing Parameters Register 2 (DTPR2) arm_A15_0: GEL Output: DDR3B_DTPR2: 0x5002C200 (Address: 0x02328050) arm_A15_0: GEL Output: tCCD[31]: Read to read and write to write command delay is 4 cycles (0) arm_A15_0: GEL Output: tRTW[30]: Read to write command delay is standard bus turn around delay +1 clock (1) arm_A15_0: GEL Output: tRTODT[29]: Read to ODT delay is 0, may come immediately after read post-amble (0) arm_A15_0: GEL Output: tDLLK[28:19]: DLL locking time is 512 cycles arm_A15_0: GEL Output: tCKE[28:19]: CKE minimum pulse width (tCKESR) is 5 cycles arm_A15_0: GEL Output: tXP[14:10]: Power down exit delay is 16 cycles arm_A15_0: GEL Output: tXS[9:0]: Self refresh exit delay is 512 cycles arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Mode Register 0 (MR0) arm_A15_0: GEL Output: DDR3B_MR0: 0x00001C70 (Address: 0x02328054) arm_A15_0: GEL Output: PD[12]: Fast power down exit (DLL on) (1) arm_A15_0: GEL Output: WR[11:9]:Write Recovery is 14 cycles (6) arm_A15_0: GEL Output: CL[6:4,2]: 11 cycles (14) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Mode Register 1 (MR1) arm_A15_0: GEL Output: DDR3B_MR1: 0x00000006 (Address: 0x02328058) arm_A15_0: GEL Output: AL[4:3]: AL Disabled (0) arm_A15_0: GEL Output: RTT[9,6,2]: ODT is RZQ/4 on SDRAM (1) arm_A15_0: GEL Output: DIC[5,1]: Output Drive is RZQ/7 on SDRAM (1) arm_A15_0: GEL Output: DE[0]: DLL Enabled on SDRAM (0) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Mode Register 2 (MR2) arm_A15_0: GEL Output: DDR3B_MR2: 0x00000018 (Address: 0x0232805C) arm_A15_0: GEL Output: RTTWR[10:9]: Dynamic ODT is Disabled (0) arm_A15_0: GEL Output: CWL[5:3]: CAS Write Latency is 8 cycles (3) arm_A15_0: GEL Output: SRT[7]: Normal Operating Temperature Range (0) arm_A15_0: GEL Output: ASR[6]: Auto Self-Refresh Power Management Disabled (0) arm_A15_0: GEL Output: PASR[2:0]: Partial Array Self-Refresh is set to Full Array (0) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Impedance Control Register 1 (ACC signals) (ZQ0CR1) arm_A15_0: GEL Output: DDR3B_ZQ0CR1: 0x0001005D (Address: 0x02328184) arm_A15_0: GEL Output: ZPROG-ODT[7:4]: On-Die Termination is set to N/A (5) arm_A15_0: GEL Output: ZPROG-ZO[3:0]: Output Impedance is set to 34ohms (13) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Impedance Control Register 1 (Data Lanes 0-3) (ZQ1CR1) arm_A15_0: GEL Output: DDR3B_ZQ1CR1: 0x0001005B (Address: 0x02328194) arm_A15_0: GEL Output: ZPROG-ODT[7:4]: On-Die Termination is set to 60ohms (5) arm_A15_0: GEL Output: ZPROG-ZO[3:0]: Output Impedance is set to 40ohms (11) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Impedance Control Register 1 (Data Lanes 4-7) (ZQ2CR1) arm_A15_0: GEL Output: DDR3B_ZQ2CR1: 0x0001005B (Address: 0x023281A4) arm_A15_0: GEL Output: ZPROG-ODT[7:4]: On-Die Termination is set to 60ohms (5) arm_A15_0: GEL Output: ZPROG-ZO[3:0]: Output Impedance is set to 40ohms (11) arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: ***************** DDR3B Leveling Errors ********************* arm_A15_0: GEL Output: PGSR0[27]: WEERR has ** No Error ** arm_A15_0: GEL Output: PGSR0[26]: REERR has ** No Error ** arm_A15_0: GEL Output: PGSR0[25]: WDERR has ** No Error ** arm_A15_0: GEL Output: PGSR0[24]: RDERR has ** Error ** arm_A15_0: GEL Output: PGSR0[23]: WLAERR has ** Error ** arm_A15_0: GEL Output: PGSR0[22]: QSGERR has ** Error ** arm_A15_0: GEL Output: PGSR0[21]: WLERR has ** No Error ** arm_A15_0: GEL Output: PGSR0[20]: ZCERR has ** No Error ** arm_A15_0: GEL Output: PGSR0[11]: WEDONE is ** Not Set ** arm_A15_0: GEL Output: PGSR0[10]: REDONE is ** Not Set ** arm_A15_0: GEL Output: PGSR0[9]: WDDONE is ** Not Set ** arm_A15_0: GEL Output: PGSR0[8]: RDDONE is ** Set ** arm_A15_0: GEL Output: PGSR0[7]: WLADONE is ** Set ** arm_A15_0: GEL Output: PGSR0[6]: QSGDONE is ** Set ** arm_A15_0: GEL Output: PGSR0[5]: WLDONE is ** Set ** arm_A15_0: GEL Output: PGSR0[4]: DIDONE is ** Set ** arm_A15_0: GEL Output: PGSR0[3]: ZCDONE is ** Not Set ** arm_A15_0: GEL Output: PGSR0[2]: DCDONE is ** Set ** arm_A15_0: GEL Output: PGSR0[1]: PLDONE is ** Set ** arm_A15_0: GEL Output: PGSR0[0]: IDONE is ** Set ** arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Leveling Errors by Byte Lane: arm_A15_0: GEL Output: Byte Lane 0: arm_A15_0: GEL Output: DX0GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX0GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX0GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX0GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX0GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX0GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX0GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 1: arm_A15_0: GEL Output: DX1GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX1GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX1GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX1GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX1GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX1GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX1GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 2: arm_A15_0: GEL Output: DX2GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX2GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX2GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX2GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX2GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX2GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX2GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 3: arm_A15_0: GEL Output: DX3GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX3GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX3GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX3GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX3GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX3GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX3GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 4: arm_A15_0: GEL Output: DX4GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX4GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX4GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX4GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX4GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX4GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX4GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 5: arm_A15_0: GEL Output: DX5GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX5GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX5GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX5GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX5GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX5GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX5GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 6: arm_A15_0: GEL Output: DX6GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX6GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX6GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX6GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX6GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX6GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX6GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 7: arm_A15_0: GEL Output: DX7GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX7GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX7GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX7GSR2[0]: RDERR has ** Error ** arm_A15_0: GEL Output: DX7GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX7GSR0[24]: QSGERR on Rank0 has ** Error ** arm_A15_0: GEL Output: DX7GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: Byte Lane 8: arm_A15_0: GEL Output: DX8GSR2[6]: WEERR has ** No Error ** arm_A15_0: GEL Output: DX8GSR2[4]: REERR has ** No Error ** arm_A15_0: GEL Output: DX8GSR2[2]: WDERR has ** No Error ** arm_A15_0: GEL Output: DX8GSR2[0]: RDERR has ** No Error ** arm_A15_0: GEL Output: DX8GSR0[25]: QSGERR on Rank1 has ** No Error ** arm_A15_0: GEL Output: DX8GSR0[24]: QSGERR on Rank0 has ** No Error ** arm_A15_0: GEL Output: DX8GSR0[6]: WLERR has ** No Error ** arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: **************************************************************************************************************** arm_A15_0: GEL Output: ***************** DDR3B Leveling Values ********************* arm_A15_0: GEL Output: Clock Period as measured by Leveling Registers: arm_A15_0: GEL Output: DX0GSR0: 0x0145A320 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 6 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX1GSR0: 0x0145A2A0 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 5 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX2GSR0: 0x0145A2A0 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 5 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX3GSR0: 0x0145A2A0 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 5 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX4GSR0: 0x0145A320 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 6 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX5GSR0: 0x0144A220 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 4 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 68 arm_A15_0: GEL Output: DX6GSR0: 0x0145A320 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 6 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX7GSR0: 0x0145A2A0 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 5 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: DX8GSR0(ECC): 0x0045A380 arm_A15_0: GEL Output: [14:7] (Write Leveling Period): 7 arm_A15_0: GEL Output: [23:16] (Read DQS Gating Period): 69 arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Delay Values from DDR3B Write Leveling Registers: arm_A15_0: GEL Output: DX0GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX0LCDLR0: 0x00000024 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 36 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX1GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX1LCDLR0: 0x00000021 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 33 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX2GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX2LCDLR0: 0x00000020 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 32 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX3GTR: 0x00005006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX3LCDLR0: 0x0000001A arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 26 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX4GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX4LCDLR0: 0x00000031 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 49 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX5GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX5LCDLR0: 0x0000002E arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 46 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX6GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX6LCDLR0: 0x00000033 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 51 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX7GTR: 0x00007006 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 3 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX7LCDLR0: 0x00000031 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 49 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: DX8GTR: 0x00005000 arm_A15_0: GEL Output: [13:12] (Rank 0 WL Cycle Latency): 1 arm_A15_0: GEL Output: [15:14] (Rank 1 WL Cycle Latency): 1 arm_A15_0: GEL Output: DX8LCDLR0: 0x00000000 arm_A15_0: GEL Output: [7:0] (Rank 0 WL Delay): 0 arm_A15_0: GEL Output: [15:8] (Rank 1 WL Delay): 0 arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Equivalent 90 degree phase shift in delay units, derived from measured period: arm_A15_0: GEL Output: DX0LCDLR1: 0x00232322 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 35 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 35 arm_A15_0: GEL Output: DX1LCDLR1: 0x00222222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 34 arm_A15_0: GEL Output: DX2LCDLR1: 0x00232222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 35 arm_A15_0: GEL Output: DX3LCDLR1: 0x00212121 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 33 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 33 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 33 arm_A15_0: GEL Output: DX4LCDLR1: 0x00222222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 34 arm_A15_0: GEL Output: DX5LCDLR1: 0x00222222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 34 arm_A15_0: GEL Output: DX6LCDLR1: 0x00232222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 35 arm_A15_0: GEL Output: DX7LCDLR1: 0x00232222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 35 arm_A15_0: GEL Output: DX8LCDLR1: 0x00222222 arm_A15_0: GEL Output: [7:0] (Write Delay Shift): 34 arm_A15_0: GEL Output: [15:8] (Read DQS Delay): 34 arm_A15_0: GEL Output: [23:16] (Read DQSN Delay): 34 arm_A15_0: GEL Output: ******************************************************** arm_A15_0: GEL Output: Delay Values from Read DQS Gating Leveling Registers: arm_A15_0: GEL Output: DX0GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX0LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX1GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX1LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX2GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX2LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX3GTR: 0x00005006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX3LCDLR2: 0x00000088 arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 136 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX4GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX4LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX5GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX5LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX6GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX6LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX7GTR: 0x00007006 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 6 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX7LCDLR2: 0x0000006B arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 107 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: DX8GTR: 0x00005000 arm_A15_0: GEL Output: [2:0] (Rank 0 DQS Gating Latency): 0 arm_A15_0: GEL Output: [5:3] (Rank 1 DQS Gating Latency): 0 arm_A15_0: GEL Output: DX8LCDLR2: 0x00000000 arm_A15_0: GEL Output: [7:0] (Rank 0 RL Delay): 0 arm_A15_0: GEL Output: [15:8] (Rank 1 RL Delay): 0 arm_A15_0: GEL Output: ****************************************************************************************************************