EMIF Configurations --------------------------------- STRUCTURE DEFINATION VALUES IN SNAPSHOT 1-DSP1 CONFIG typedef struct { / ** Chip Enable2 Configuration register * / volatile Uint32 CE2CFG; 0x04190847, / ** Chip Enable3 Configuration register * / volatile Uint32 CE3CFG; 0x8000000E, / ** Chip Enable4 Configuration register * / volatile Uint32 CE4CFG; 0X021510AA, /*CE4 config reg */ //0x8000000E, //change 19/11/2014 / ** Chip Enable5 Configuration register * / volatile Uint32 CE5CFG; 0x8000000E, //0x010C9066, //0x031598AE, commented 30/10/2014 change to 0x01064866 (90%),0x010C9066(100%) / ** Asynchronous Wait Cycle Configuration register * /volatile Uint32 AWCC; 0x00000000, /*AWCC reg val --> values according default values for async read write in csl_emifa.h */ //0x40000180 ,30/10/2014 / ** Interrupt Raw Register * / volatile Uint32 INTRAW; 0x00000000, /*INTRAW reg val --> value is according to CSL's example default value */ / ** Interrupt Masked Register * / volatile Uint32 INTMSK; 0x00000000, /*INTMSK reg val --> value is according to CSL's example default value */ / ** Interrupt Mask Set Register * /volatile Uint32 INTMSKSET; 0x00000000, /*INTMSKSET reg val --> value is according to CSL's example default value */ / ** Interrupt Mask Clear Register * / volatile Uint32 INTMSKCLR; 0x00000000, /*INTMSKCLR reg val --> value is according to CSL's example default value */ / ** Burst Priority Register * / volatile Uint32 BPRIO; 0x000000FF, /*BPRIO reg val --> value is according to CSL's example default value */ } CSL_EmifaConfig; ________________________________________________________________________________________________________ DSP1 EMIF CONFIGURATION VALUES AGAIN FOR REFERENCE 0x04190847, 0x8000000E, 0X021510AA, /*CE4 config reg */ //0x8000000E, //change 19/11/2014 0x8000000E, //0x010C9066, //0x031598AE, commented 30/10/2014 change to 0x01064866 (90%),0x010C9066(100%) 0x00000000, /*AWCC reg val --> values according default values for async read write in csl_emifa.h */ //0x40000180 ,30/10/2014 0x00000000, /*INTRAW reg val --> value is according to CSL's example default value */ 0x00000000, /*INTMSK reg val --> value is according to CSL's example default value */ 0x00000000, /*INTMSKSET reg val --> value is according to CSL's example default value */ 0x00000000, /*INTMSKCLR reg val --> value is according to CSL's example default value */ 0x000000FF, /*BPRIO reg val --> value is according to CSL's example default value */ ___________________________________________________________________________________________________________ CHIP ENABLE 2 CONFIGURATIONS BITS SEPERATE FOR VALUE 0x04190847 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 1 1 FIELD BITS VAL DETAILS OF THE FIELD ---------------------------------------------------------------------------------------------------------- ASIZE 1-0 3 64BIT - Asynchronous Memory Size. Defines the width of the asynchronous device's data bus. 0 8-bit data bus. 1 16-bit data bus. 2 32-bit data bus. 3 64-bit data bus. R_HOLD 4-2 1 Read hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], BE[7:0], and CEn are held after AOE has been deasserted, minus one cycle. R_STROBE 10-5 2 Read strobe width. Number of ECLKOUT cycles for which AOE is held active, minus one cycle. R_SETUP 14-11 1 Read setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], BE[7:0], and CEn being set to AOE asserted, minus one cycle. W_HOLD 17-15 2 Write hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn are held after AWE has been deasserted, minus one cycle W_STROBE 23-18 6 Write strobe width. Number of ECLKOUT cycles for which AWE is held active, minus one cycle. W_SETUP 27-24 4 Write setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn being set to AWE asserted, minus one cycle. AE 28 0 Asynchronous ready input enable. Set to 1 to enable the asynchronous ready (ARDY) input pin during accesses to the CEn space. When enabled, the ARDY pin can be used to extend the strobe period during asynchronous accesses. 1 ARDY pin enabled 0 ARDY pin disabled BWEM 29 0 WE Strobe mode enable. When set to 1, the BE[7:0] output pins will act as active low byte write enables when accessing CEn space. When cleared to 0, the BE[7:0] output pins will act as active low byte enables when accessing CEn. 1 WE Strobe mode enabled 0 WE Strobe mode disabled SS 30 0 Select Strobe mode enable. When set to 1, the CEn pin will have read and write strobe timing. 1 Select strobe mode enabled 0 Select strobe mode disabled SSEL 31 0 Synchronous/asynchronous memory select. This bit specifies whether CEn is configured for synchronous or asynchronous memory accesses. The other fields in this table define the bits in the CEnCFG when SSEL is cleared to 0 (asynchronous memory mode). 1 Synchronous memory mode 0 Asynchronous memory mode ___________________________________________________________________________________________________________ ########################################################################################################### ___________________________________________________________________________________________________________ CHIP ENABLE 3 CONFIGURATIONS BITS SEPERATE FOR VALUE 0x8000000E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 FIELD BITS VAL DETAILS OF THE FIELD ---------------------------------------------------------------------------------------------------------- ASIZE 1-0 2 32BIT - Asynchronous Memory Size. Defines the width of the asynchronous device's data bus. 0 8-bit data bus. 1 16-bit data bus. 2 32-bit data bus. 3 64-bit data bus. R_HOLD 4-2 3 Read hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], BE[7:0], and CEn are held after AOE has been deasserted, minus one cycle. R_STROBE 10-5 0 Read strobe width. Number of ECLKOUT cycles for which AOE is held active, minus one cycle. R_SETUP 14-11 0 Read setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], BE[7:0], and CEn being set to AOE asserted, minus one cycle. W_HOLD 17-15 0 Write hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn are held after AWE has been deasserted, minus one cycle W_STROBE 23-18 0 Write strobe width. Number of ECLKOUT cycles for which AWE is held active, minus one cycle. W_SETUP 27-24 0 Write setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn being set to AWE asserted, minus one cycle. AE 28 0 Asynchronous ready input enable. Set to 1 to enable the asynchronous ready (ARDY) input pin during accesses to the CEn space. When enabled, the ARDY pin can be used to extend the strobe period during asynchronous accesses. 1 ARDY pin enabled 0 ARDY pin disabled BWEM 29 0 WE Strobe mode enable. When set to 1, the BE[7:0] output pins will act as active low byte write enables when accessing CEn space. When cleared to 0, the BE[7:0] output pins will act as active low byte enables when accessing CEn. 1 WE Strobe mode enabled 0 WE Strobe mode disabled SS 30 0 Select Strobe mode enable. When set to 1, the CEn pin will have read and write strobe timing. 1 Select strobe mode enabled 0 Select strobe mode disabled SSEL 31 1 Synchronous/asynchronous memory select. This bit specifies whether CEn is configured for synchronous or asynchronous memory accesses. The other fields in this table define the bits in the CEnCFG when SSEL is cleared to 0 (asynchronous memory mode). 1 Synchronous memory mode 0 Asynchronous memory mode _______________________________________________________________________________________________________________ ########################################################################################################### ___________________________________________________________________________________________________________ CHIP ENABLE 4 CONFIGURATIONS BITS SEPERATE FOR VALUE 0X021510AA 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 0 FIELD BITS VAL DETAILS OF THE FIELD ---------------------------------------------------------------------------------------------------------- ASIZE 1-0 2 32BIT - Asynchronous Memory Size. Defines the width of the asynchronous device's data bus. 0 8-bit data bus. 1 16-bit data bus. 2 32-bit data bus. 3 64-bit data bus. R_HOLD 4-2 2 Read hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], BE[7:0], and CEn are held after AOE has been deasserted, minus one cycle. R_STROBE 10-5 5 Read strobe width. Number of ECLKOUT cycles for which AOE is held active, minus one cycle. R_SETUP 14-11 2 Read setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], BE[7:0], and CEn being set to AOE asserted, minus one cycle. W_HOLD 17-15 2 Write hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn are held after AWE has been deasserted, minus one cycle W_STROBE 23-18 5 Write strobe width. Number of ECLKOUT cycles for which AWE is held active, minus one cycle. W_SETUP 27-24 2 Write setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn being set to AWE asserted, minus one cycle. AE 28 0 Asynchronous ready input enable. Set to 1 to enable the asynchronous ready (ARDY) input pin during accesses to the CEn space. When enabled, the ARDY pin can be used to extend the strobe period during asynchronous accesses. 1 ARDY pin enabled 0 ARDY pin disabled BWEM 29 0 WE Strobe mode enable. When set to 1, the BE[7:0] output pins will act as active low byte write enables when accessing CEn space. When cleared to 0, the BE[7:0] output pins will act as active low byte enables when accessing CEn. 1 WE Strobe mode enabled 0 WE Strobe mode disabled SS 30 0 Select Strobe mode enable. When set to 1, the CEn pin will have read and write strobe timing. 1 Select strobe mode enabled 0 Select strobe mode disabled SSEL 31 0 Synchronous/asynchronous memory select. This bit specifies whether CEn is configured for synchronous or asynchronous memory accesses. The other fields in this table define the bits in the CEnCFG when SSEL is cleared to 0 (asynchronous memory mode). 1 Synchronous memory mode 0 Asynchronous memory mode ______________________________________________________________________________________________________________ ########################################################################################################### ___________________________________________________________________________________________________________ CHIP ENABLE 5 CONFIGURATIONS BITS SEPERATE FOR VALUE 0x8000000E 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 FIELD BITS VAL DETAILS OF THE FIELD ---------------------------------------------------------------------------------------------------------- ASIZE 1-0 2 32BIT - Asynchronous Memory Size. Defines the width of the asynchronous device's data bus. 0 8-bit data bus. 1 16-bit data bus. 2 32-bit data bus. 3 64-bit data bus. R_HOLD 4-2 3 Read hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], BE[7:0], and CEn are held after AOE has been deasserted, minus one cycle. R_STROBE 10-5 0 Read strobe width. Number of ECLKOUT cycles for which AOE is held active, minus one cycle. R_SETUP 14-11 0 Read setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], BE[7:0], and CEn being set to AOE asserted, minus one cycle. W_HOLD 17-15 0 Write hold width. Number of ECLKOUT cycles for which EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn are held after AWE has been deasserted, minus one cycle W_STROBE 23-18 0 Write strobe width. Number of ECLKOUT cycles for which AWE is held active, minus one cycle. W_SETUP 27-24 0 Write setup width. Number of ECLKOUT cycles from EA[19:0], BA[1:0], D[63:0], BE[7:0], and CEn being set to AWE asserted, minus one cycle. AE 28 0 Asynchronous ready input enable. Set to 1 to enable the asynchronous ready (ARDY) input pin during accesses to the CEn space. When enabled, the ARDY pin can be used to extend the strobe period during asynchronous accesses. 1 ARDY pin enabled 0 ARDY pin disabled BWEM 29 0 WE Strobe mode enable. When set to 1, the BE[7:0] output pins will act as active low byte write enables when accessing CEn space. When cleared to 0, the BE[7:0] output pins will act as active low byte enables when accessing CEn. 1 WE Strobe mode enabled 0 WE Strobe mode disabled SS 30 0 Select Strobe mode enable. When set to 1, the CEn pin will have read and write strobe timing. 1 Select strobe mode enabled 0 Select strobe mode disabled SSEL 31 1 Synchronous/asynchronous memory select. This bit specifies whether CEn is configured for synchronous or asynchronous memory accesses. The other fields in this table define the bits in the CEnCFG when SSEL is cleared to 0 (asynchronous memory mode). 1 Synchronous memory mode 0 Asynchronous memory mode ______________________________________________________________________________________________________________ AWCC ASYNCHRONOUS WAIT CYCLE CONFIGURATION REGISTER * /VOLATILE UINT32 AWCC; VALUE IS 0X0000000000 FIELD BITS VAL DETAILS OF THE FIELD ---------------------------------------------------------------------------------------------------------------- MAX_EXT_WAIT 7-0 0 Maximum Extended Wait cycles. The value in this field defines the number of 16 EMIF cycle periods the EMIF will wait for an extended asynchronous cycle before the cycle is terminated TA 10-8 0 Turn Around cycles. Number of ECLKOUT cycles between the end of one asynchronous memory access and the start of another asynchronous memory access, minus two cycles Reserved 29-11 0 Reserved AP 30 0 Asynchronous ready (ARDY) pin polarity. Defines the polarity of the ARDY pin. 1 ARDY pin is active-high (strobe period extended when ARDY is high) 0 ARDY pin is active-low (strobe period extended when ARDY is low) Reserved 31 0 Reserved _______________________________________________________________________________________________________________ /*INTRAW REG VAL --> VALUE IS ACCORDING TO CSL'S EXAMPLE DEFAULT VALUE */ VALUE IS 0X0000000000 FIELD BITS VAL DETAILS OF THE FIELD --------------------------------------------------------------------------------------------------------------- Reserved 31-1 0 Reserved AT 0 0 Asynchronous timeout interrupt. Set to 1 by the EMIF to indicate that the ARDY pin did not go inactive within the number of cycles defined by the MAX_EXT_WAIT field in the Async Wait Cycle Configuration register (AWCC). Writing a 1 will clear this bit as well as the AT_MASKED bit in the Interrupt Masked register (INTMSK). Writing a 0 has no effect. 1 An asynchronous access timeout has occurred. 0 An asynchronous access timeout has not occurred. _______________________________________________________________________________________________________________ /*INTMSK REG VAL --> VALUE IS ACCORDING TO CSL'S EXAMPLE DEFAULT VALUE */ VALUE IS 0X0000000000 FIELD BITS VAL DETAILS OF THE FIELD --------------------------------------------------------------------------------------------------------------- Reserved 31-1 0 Reserved AT_MASKED 0 0 Asynchronous timeout interrupt masked. Set to 1 by the EMIF to indicate that the ARDY pin did not go inactive within the number of cycles defined by the MAX_EXT_WAIT field in the Asynchronous Wait Cycle Configuration register (AWCC) only if the AT_MASK_SET bit in the Interrupt Mask Set register is set to 1. Writing a 1 will clear this bit as well as the AT bit in the Interrupt Raw register (INTRAW). Writing a 0 has no effect. 1 An asynchronous access timeout has occurred. 0 An asynchronous access timeout has not occurred. _______________________________________________________________________________________________________________ /*INTMSKSET REG VAL --> VALUE IS ACCORDING TO CSL'S EXAMPLE DEFAULT VALUE */ VALUE IS 0X0000000000 FIELD BITS VAL DETAILS OF THE FIELD --------------------------------------------------------------------------------------------------------------- Reserved 31-1 0 Reserved AT_MASK_SET 0 0 Mask set for AT_MASKED bit in the Interrupt Masked register. Writing a 1 to this bit will enable the interrupt and set this bit as well as the AT_MASK_CLR bit in the Interrupt Mask Set register. Writing a 0 has no effect. 1 The asynchronous access timeout interrupt is enabled. 0 The asynchronous access timeout interrupt is disabled. _______________________________________________________________________________________________________________ /*INTMSKCLR REG VAL --> VALUE IS ACCORDING TO CSL'S EXAMPLE DEFAULT VALUE */ VALUE IS 0X0000000000 FIELD BITS VAL DETAILS OF THE FIELD --------------------------------------------------------------------------------------------------------------- Reserved 31-1 0 Reserved AT_MASK_CLR 0 0 Mask clear for AT_MASKED bit in the Interrupt Masked register. Writing a 1 to this bit will disable the interrupt and clear this bit as well as the AT_MASK_SET bit in the Interrupt Mask Set register. Writing a 0 has no effect. 1 The asynchronous access timeout interrupt is enabled. 0 The asynchronous access timeout interrupt is disabled. _______________________________________________________________________________________________________________ /*BPRIO REG VAL --> VALUE IS ACCORDING TO CSL'S EXAMPLE DEFAULT VALUE */ VALUE IS 0X00000000FF FIELD BITS VAL DETAILS OF THE FIELD --------------------------------------------------------------------------------------------------------------- Reserved 31-8 0 Reserved PRIO_RAISE 7-0 FF Number of memory transfers after which the EMIF will elevate the priority of the oldest command in the command FIFO. Setting this field to FFh disables this feature, thereby allowing old commands to stay in the FIFO indefinitely. 0 1 memory transfer. 1 2 memory transfers. 2 3 memory transfers. 3-FEh 4-FFh memory transfers. FFh Feature disabled, commands can stay in command FIFO indefinitely _______________________________________________________________________________________________________________