/**
 * These arguments were used when this file was generated. They will be automatically applied on subsequent loads
 * via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
 * @cliArgs --device "J7200_DRA821_SR1.0_alpha" --part "Default" --package "ALM" --product "TDA4x_DRA8x_AM67x-AM69x_DDR_Config@0.12.00.0000"
 * @v2CliArgs --device "DRA821U" --package "FCBGA (ALM)" --product "TDA4x_DRA8x_AM67x-AM69x_DDR_Config@0.12.00.0000"
 * @versions {"tool":"1.27.0+4565"}
 */

/**
 * Import the modules used in this configuration.
 */
const DDRSS = scripting.addModule("/DDRSS");

/**
 * Write custom configuration values to the imported modules.
 */
DDRSS.lpddr4.$name                               = "jacinto_lpddr4_DDRSS_LPDDR40";
DDRSS.lpddr4.config_dram_mr1_nWR_FS2             = 30;
DDRSS.lpddr4.config_dram_mr2_rl_FS2              = 32;
DDRSS.lpddr4.config_dram_mr2_wl_FS2              = 14;
DDRSS.lpddr4.config_dram_odtlon_FS2              = 6;
DDRSS.lpddr4.config_dram_odtloff_FS2             = 24;
DDRSS.lpddr4.config_dram_tREFIpb_ns              = 244;
DDRSS.lpddr4.config_dram_tRRD_ns                 = 11.875;
DDRSS.lpddr4.config_dram_tFAW_ns                 = 40;
DDRSS.lpddr4.system_cfg_dram_density             = 16;
DDRSS.lpddr4.config_dram_tWR_ns                  = 18;
DDRSS.lpddr4.config_dram_tWTR_ns                 = 10;
DDRSS.lpddr4.config_dram_tRFCab_ns               = 380;
DDRSS.lpddr4.config_dram_tRFCpb_ns               = 190;
DDRSS.lpddr4.config_dram_tXSR_ns                 = 387.5;
DDRSS.lpddr4.config_dram_tREFIab_ns              = 1952;
DDRSS.lpddr4.config_dram_tRASmax_ns              = 17568;
DDRSS.lpddr4.config_io_cell_enslicen_drv_dl0_dq  = "48 Ohm";
DDRSS.lpddr4.config_dram_tRCD_ns                 = 19.875;
DDRSS.lpddr4.config_dram_tRASmin_ns              = 43.875;
DDRSS.lpddr4.config_dram_tRPab_ns                = 22.875;
DDRSS.lpddr4.config_dram_tRPpb_ns                = 19.875;
DDRSS.lpddr4.config_dram_tDQSCKmax_ns            = 3.6;
DDRSS.lpddr4.config_io_cell_enslicen_drv_dl0_dqs = "48 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_odt_dl0_dq  = "40 Ohm";
DDRSS.lpddr4.config_io_cell_enslicen_odt_dl0_dqs = "40 Ohm";
DDRSS.lpddr4.config_dram_mr14_vref_dq_FS2        = 22;
DDRSS.lpddr4.config_dram_mr12_vref_ca_FS2        = 23.2;
DDRSS.lpddr4.config_dram_mr11_dq_odt_FS2         = "RZQ/5";
DDRSS.lpddr4.config_dram_mr3_pdds_FS2            = "RZQ/6";
DDRSS.lpddr4.config_dram_mr22_odte_cs_FS2        = "Disable";
DDRSS.lpddr4.config_dram_mr22_soc_odt_FS2        = "RZQ/6";