void SYS_InitGPMC(void)
{
  //Reset GPMC
  //SYS_GpmcRegs->ERR_TYPE = 0;
  CSL_FINST(SYS_GpmcRegs->SYSCONFIG,GPMC_SYSCONFIG_SOFTRESET, RESET);

  while((SYS_GpmcRegs->SYSSTATUS & CSL_GPMC_SYSSTATUS_RESETDONE_MASK) != CSL_GPMC_SYSSTATUS_RESETDONE_RSTDONE)
  {
    //wait till reset is done
  }
  //disable all irq
  SYS_GpmcRegs->IRQENABLE = 0x00000000;
  //no timeout
  SYS_GpmcRegs->TIMEOUT_CONTROL = 0x00000000;
  //wait active low and disable force posted write
  SYS_GpmcRegs->CONFIG = 0x00000000;
  //device options
  //GPMC_CLK frequency = GPMC_FCLK frequency
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_GPMCFCLKDIVIDER,DIVBY1); // div 2 = 133Mhz this must coresponde to clk_out1!!!
  //x1 latencies
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_TIMEPARAGRANULARITY,X2);
  //Nonmultiplexed attached device
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_MUXADDDATA,NONMUX);
  //NOR flash-like, asynchronous and synchronous devices
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_DEVICETYPE,NORLIKE);
  //16 bit
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_DEVICESIZE,SIXTEENBITS);
  //Wait input pin is WAIT0
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WAITPINSELECT,W0);
  //Wait pin is monitored with valid data.
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WAITMONITORINGTIME,RESETVAL);
  //Wait pin is not monitored for write accesses.
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WAITWRITEMONITORING,WNOTMONIT);
  //Wait pin is not monitored for read accesses.
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WAITREADMONITORING,WNOTMONIT);
  //device page (burst) length: 4 words
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH,FOUR);
  //First rising edge of GPMC_CLK at start access time
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_CLKACTIVATIONTIME,ATSTART);
  //Write synchronous
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WRITETYPE,WRASYNC);
  //Single access
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WRITEMULTIPLE,WRSINGLE);
  //Single access
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_READTYPE,RDASYNC);
  //Single access
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_READMULTIPLE,RDSINGLE);
  //Synchronous wrapping burst not supported
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG1,GPMC_CONFIG1_WRAPBURST,WRAPNOTSUPP);
  //CS Timing
  //no delays
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG2,GPMC_CONFIG2_CSONTIME,0);
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG2,GPMC_CONFIG2_CSEXTRADELAY,NOTDELAYED);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG2,GPMC_CONFIG2_CSRDOFFTIME,GPMC_ACCESS_TIME);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG2,GPMC_CONFIG2_CSWROFFTIME,GPMC_ACCESS_TIME);
  //ADV Timing
  //no delays
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVEXTRADELAY,NOTDELAYED);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVAADMUXONTIME,0);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVONTIME,0);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVWROFFTIME,GPMC_ACCESS_TIME);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVRDOFFTIME,GPMC_ACCESS_TIME);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVAADMUXRDOFFTIME,GPMC_ACCESS_TIME);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG3,GPMC_CONFIG3_ADVAADMUXWROFFTIME,GPMC_ACCESS_TIME);
  //OE and WE Timing
  SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG4 = 0x00000000;
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG4,GPMC_CONFIG4_OEONTIME,0);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG4,GPMC_CONFIG4_OEOFFTIME,GPMC_ACCESS_TIME);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG4,GPMC_CONFIG4_WEONTIME,0);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG4,GPMC_CONFIG4_WEOFFTIME,GPMC_ACCESS_TIME);
  //RD cycle and WR cycle Timing
  //Set read and write cycle time to max for first testing
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG5,GPMC_CONFIG5_WRCYCLETIME,GPMC_ACCESS_TIME);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG5,GPMC_CONFIG5_RDCYCLETIME,GPMC_ACCESS_TIME);
  //no pageburst and read access delays
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG5,GPMC_CONFIG5_PAGEBURSTACCESSTIME,0x0U);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG5,GPMC_CONFIG5_RDACCESSTIME,GPMC_ACCESS_TIME-GPMC_RDDATAVALID);
  //WR accestime
  //add one clock cycle delay between reads
  SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG6 = 0;
  CSL_FINST(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG6,GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,C2CDELAY);
  CSL_FINS(SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG6,GPMC_CONFIG6_CYCLE2CYCLEDELAY,0x1U);
  //set cs size to 128MiB and base address to 0x8000000 and enable cs
  SYS_GpmcRegs->CONFIG_BLOCK[GPMC_FPGA_CS_NR].CONFIG7 = 0x00000848;

}