struct tisci_msg_rm_irq_set_req      rmIrqReq;   
struct tisci_msg_rm_irq_set_resp     rmIrqResp;   
int32_t ret = UART_SUCCESS;

(void)memset (&rmIrqReq, 0, sizeof(rmIrqReq));   
     
rmIrqReq.secondary_host = TISCI_MSG_VALUE_RM_UNUSED_SECONDARY_HOST;     
rmIrqReq.src_id = TISCI_DEV_UARTx; /* 'x' can be '3' to '9', depending on UART instance */       
rmIrqReq.src_index = 0; 
        
/* Set the destination interrupt */     
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_ID_VALID;     
rmIrqReq.valid_params |= TISCI_MSG_VALUE_RM_DST_HOST_IRQ_VALID;

/* Set the destination based on the core */      
rmIrqReq.dst_id       = TISCI_DEV_R5FSSx_COREy; /* 'x'='0'/'1' 'y'='0'/'1', depending on MAIN R5F core */       
rmIrqReq.dst_host_irq = <intNum>; /* intNum can be any # from '256' to '383' for "CORE0", and from '384' to '511' for "CORE1". This is related to the resource partitioning in BoardCfg. */

retVal = Sciclient_rmIrqSet((const struct tisci_msg_rm_irq_set_req*)&rmIrqReq, &rmIrqResp, SCICLIENT_SERVICE_WAIT_FOREVER);
/* Make sure retVal is success */