** DMTimer2 in seconds: 164 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 168 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 169 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 170 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 171 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 164 --> First overflow of DMTIMER2 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 168 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 169 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 170 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 171 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 164 --> Second overflow of DMTIMER2 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 168 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 169 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 170 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 171 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 164 --> Third overflow of DMTIMER2 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 168 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 169 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 170 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 171 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 164 --> Fourth overflow of DMTIMER2 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 168 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 169 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 170 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 171 ** DMTimer3 ticks (TCCR Register): 0x00000000 ** DMTimer2 in seconds: 164 --> Fifth overflow of DMTIMER2 ** DMTimer3 ticks (TCCR Register): 0x00000001 --> DMTIMER3 is incremented ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 168 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 169 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 170 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 171 ** DMTimer3 ticks (TCCR Register): 0x00000001 ** DMTimer2 in seconds: 164 ** DMTimer3 ticks (TCCR Register): 0x00000002 ** DMTimer2 in seconds: 165 ** DMTimer3 ticks (TCCR Register): 0x00000002 ** DMTimer2 in seconds: 166 ** DMTimer3 ticks (TCCR Register): 0x00000002 ** DMTimer2 in seconds: 167 ** DMTimer3 ticks (TCCR Register): 0x00000002