CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence In Progress... <<<--- CortexA15_0: GEL Output: --->>> AM572x Cortex A15 Startup Sequence DONE! <<<--- CortexA15_0: GEL Output: --->>> AM572x GP EVM <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence Begins ... <<<--- CortexA15_0: GEL Output: --->>> I2C Init <<<--- CortexA15_0: GEL Output: --->>> AM572x Begin MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x End MMC2 Pad Configuration <<<--- CortexA15_0: GEL Output: --->>> AM572x PG2.0 GP device <<<--- CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPPNOM in progress... <<<--- CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: Cortex A15 DPLL is already locked, now unlocking... CortexA15_0: GEL Output: Cortex A15 DPLL OPP 0 is DONE! CortexA15_0: GEL Output: IVA DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: IVA DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PER DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: PER DPLL already locked, now unlocking CortexA15_0: GEL Output: PER DPLL OPP 0 is DONE! CortexA15_0: GEL Output: CORE DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: CORE DPLL OPP already locked, now unlocking.... CortexA15_0: GEL Output: CORE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: ABE DPLL OPP 0 clock config in progress... CortexA15_0: GEL Output: ABE DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GMAC DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GMAC DPLL OPP 0 is DONE! CortexA15_0: GEL Output: GPU DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: GPU DPLL OPP 0 is DONE! CortexA15_0: GEL Output: DSP DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: DSP DPLL OPP 0 is DONE! CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 clock config is in progress... CortexA15_0: GEL Output: PCIE_REF DPLL OPP 0 is DONE! CortexA15_0: GEL Output: --->>> PRCM Clock Configuration for OPP 0 is DONE! <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules in progress... <<<--- CortexA15_0: GEL Output: --->>> PRCM Configuration for all modules is DONE! <<<--- CortexA15_0: GEL Output: --->>> DDR3 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in progress... CortexA15_0: GEL Output: DDR DPLL clock config for 532MHz is in DONE! CortexA15_0: GEL Output: Launch full leveling CortexA15_0: GEL Output: ERROR: HW-Leveling time-out CortexA15_0: GEL Output: Two EMIFs in non interleaved mode (2GB total) CortexA15_0: GEL Output: --->>> DDR3 Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<---- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- CortexA15_0: GEL Output: --->>> AM572x Target Connect Sequence DONE !!!!! <<<--- CortexA15_0: GEL Output: --->>> Mapping TIMER suspend sources to default cores <<<<<<---- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> IPU2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP1SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP1SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> DSP2SS Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: DEBUG: Checking for data integrity in DSPSS L2RAM ... CortexA15_0: GEL Output: DEBUG: Data integrity check in GEM L2RAM is sucessful! CortexA15_0: GEL Output: --->>> DSP2SS Initialization is DONE! <<<--- CortexA15_0: GEL Output: --->>> IVAHD Initialization is in progress ... <<<--- CortexA15_0: GEL Output: DEBUG: Clock is active ... CortexA15_0: GEL Output: --->>> IVAHD Initialization is DONE! ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in progress ... <<<--- CortexA15_0: GEL Output: --->>> PRUSS 1 and 2 Initialization is in complete ... <<<--- CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 0: 0x00000000 CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 1: 0x00000000 CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 2: 0x00000000 CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 3: 0x00000000 CortexA15_0: GEL Output: EMIF_PHY_FIFO_WE_SLAVE_RATIO Macro 4: 0x00000000 CortexA15_0: GEL Output: CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 0: 0x0000007F CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 1: 0x0000007F CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 2: 0x0000007F CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 3: 0x0000007F CortexA15_0: GEL Output: EMIF_PHY_RD_DQS_SLAVE_RATIO Macro 4: 0x0000007F CortexA15_0: GEL Output: CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 0: 0x00000077 CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 1: 0x00000077 CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 2: 0x00000077 CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 3: 0x00000077 CortexA15_0: GEL Output: EMIF_PHY_WR_DATA_SLAVE_RATIO Macro 4: 0x00000077 CortexA15_0: GEL Output: CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 0: 0x00000057 CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 1: 0x00000057 CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 2: 0x00000057 CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 3: 0x00000057 CortexA15_0: GEL Output: EMIF_PHY_WR_DQS_SLAVE_RATIO Macro 4: 0x00000057 CortexA15_0: GEL Output: CortexA15_0: GEL Output: ------------------------------------------------------- CortexA15_0: GEL Output: PRCM State of all modules on the device CortexA15_0: GEL Output: ------------------------------------------------------- CortexA15_0: GEL Output: Module : DMA_SYSTEM (CD_DMA, PD_CORE) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DSP1 (CD_DSP1, PD_DSP1) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DSP2 (CD_DSP2, PD_DSP2) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : BB2D (CD_DSS, PD_DSS) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DSS (CD_DSS, PD_DSS) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DLL (CD_EMIF, PD_CORE) CortexA15_0: GEL Output: Module State : Determined by Clock State CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DMM (CD_EMIF, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : EMIF1 (CD_EMIF, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : EMIF2 (CD_EMIF, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : EMIF_OCP_FW (CD_EMIF, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : CPGMAC (CD_GMAC, PD_L3INIT) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPU (CD_GPU, PD_GPU) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : OFF CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : I2C5 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP1 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER5 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER6 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER7 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER8 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART6 (CD_IPU, PD_IPU) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : IPU1 (CD_IPU1, PD_IPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : IPU2 (CD_IPU2, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : IVA (CD_IVA, PD_IVA) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SL2 (CD_IVA, PD_IVA) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : IEEE1500_2_OCP (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MMC1 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MMC2 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SATA (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCP2SCP1 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCP2SCP3 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : USB_OTG_SS1 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : USB_OTG_SS2 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : USB_OTG_SS3 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : USB_OTG_SS4 (CD_L3INIT, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : CTRL_MODULE_BANDGAP (CD_L3INSTR, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DLL_AGING (CD_L3INSTR, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L3_INSTR (CD_L3INSTR, PD_CORE) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L3_MAIN_2 (CD_L3INSTR, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCP_WP_NOC (CD_L3INSTR, PD_CORE) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPMC (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L3_MAIN_1 (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MMU_EDMA (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MMU_PCIESS (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCMC_RAM1 (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCMC_RAM2 (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCMC_RAM3 (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TPCC (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TPTC1 (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TPTC2 (CD_L3MAIN1, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L4_CFG (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : OCP2SCP2 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SAR_ROM (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SPINLOCK (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : IO_DELAY_BLOCK (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX1 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX10 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX11 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX12 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX13 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX2 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX3 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX4 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX5 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX6 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX7 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX8 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MAILBOX9 (CD_L4CFG, PD_CORE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : I2C1 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : I2C2 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : I2C3 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : I2C4 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L4_PER1 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER10 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER11 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER2 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER3 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER4 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER9 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : ELM (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : HDQ1W (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCSPI1 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCSPI2 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCSPI3 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCSPI4 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART1 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART2 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART3 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART4 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART5 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO2 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO3 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO4 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO5 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO6 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO7 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO8 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MMC3 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MMC4 (CD_L4PER, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DCAN2 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L4_PER2 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART7 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART8 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART9 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PRUSS1 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PRUSS2 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : STANDBY CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE AUTO CLOCK GATED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP2 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP3 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP4 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP5 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP6 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP7 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MCASP8 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PWMSS1 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PWMSS2 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PWMSS3 (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : QSPI (CD_L4PER2, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L4_PER3 (CD_L4PER3, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER13 (CD_L4PER3, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER14 (CD_L4PER3, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER15 (CD_L4PER3, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER16 (CD_L4PER3, PD_L4PER) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : AES1 (CD_L4SEC, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : AES2 (CD_L4SEC, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DES3DES (CD_L4SEC, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : RNG (CD_L4SEC, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SHA2MD51 (CD_L4SEC, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SHA2MD52 (CD_L4SEC, PD_L4PER) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MPU (CD_MPU, PD_MPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MPU_MPU_DBG (CD_MPU, PD_MPU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PCIESS1 (CD_PCIE, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : PCIESS2 (CD_PCIE, PD_L3INIT) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : RTCSS (CD_RTC, PD_RTC) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : VIP1 (CD_CAM, PD_CAM) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : VIP2 (CD_CAM, PD_CAM) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : VIP3 (CD_CAM, PD_CAM) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : VPE (CD_VPE, PD_VPE) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DEBUG_LOGIC (CD_EMU, PD_EMU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : MPU_EMU_DBG (CD_EMU, PD_EMU) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : COUNTER_32K (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : CTRL_MODULE_WKUP (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : Determined by Clock State CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : DCAN1 (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : GPIO1 (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : IO_SRCOMP_WKUP (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : Determined by Clock State CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : KBD (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : L4_WKUP (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : SAR_RAM (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER1 (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : TIMER12 (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : UART10 (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : DISABLED CortexA15_0: GEL Output: Clock State : OFF CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE DISABLED CortexA15_0: GEL Output: ========================================== CortexA15_0: GEL Output: Module : WD_TIMER2 (CD_WKUPAON, PD_WKUPAON) CortexA15_0: GEL Output: Module State : ON CortexA15_0: GEL Output: Clock State : ON CortexA15_0: GEL Output: Power State : ALWAYS ON CortexA15_0: GEL Output: Final State : MODULE ALWAYS ENABLED CortexA15_0: GEL Output: ==========================================