__________________________________________________________________________________________________________________________________________________________________________________________________ PLL COMPARISION ____________________________________________________________________________________________________________________________________________________________________________________________________ MCSDK kernel prints :- MAIN_PLL init [ 0.000000] LWS PLL has_control [ 0.000000] LWS pllm 0 pllm_lower_mask 3f pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7f000LWS clk_register_keystone_pll [ 0.000000] LWS clock NAME mainpllclk [ 0.000000] LWS mult == 30 val == 3800901f [ 0.000000] LWS PLL has no control [ 0.000000] LWS PLLMAIN fixed_postdiv not found [ 0.000000] LWS pllm 0 pllm_lower_mask 0 pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0LWS clk_register_keystone_pll [ 0.000000] LWS clock NAME armpllclk [ 0.000000] LWS mult == 0 val == 17000bc4 [ 0.000000] LWS PLL has no control [ 0.000000] LWS PLLMAIN fixed_postdiv not found [ 0.000000] LWS pllm 0 pllm_lower_mask 0 pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0LWS clk_register_keystone_pll [ 0.000000] LWS clock NAME ddr3a_clk [ 0.000000] LWS mult == 0 val == 92804c0 [ 0.000000] LWS PLL has no control [ 0.000000] LWS PLLMAIN fixed_postdiv not found [ 0.000000] LWS pllm 0 pllm_lower_mask 0 pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0LWS clk_register_keystone_pll [ 0.000000] LWS clock NAME ddr3b_clk [ 0.000000] LWS mult == 0 val == 98804c0 [ 0.000000] LWS PLL has no control [ 0.000000] LWS PLLMAIN fixed_postdiv not found [ 0.000000] LWS pllm 0 pllm_lower_mask 0 pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0LWS clk_register_keystone_pll [ 0.000000] LWS clock NAME papllclk [ 0.000000] LWS clock NAME refclk-main [ 0.000000] LWS mult == 30 val == 3800901f [ 0.000000] Main PLL clk (1200000000 Hz), parent (122880000 Hz),postdiv = 2, mult = 624, prediv = 31 [ 0.000000] LWS clock NAME refclk-arm [ 0.000000] LWS mult == 0 val == 17000bc4 [ 0.000000] Generic PLL clk (1200000000 Hz), parent (125000000 Hz),postdiv = 1, mult = 47, prediv = 4 [ 0.000000] LWS clock NAME refclk-pass [ 0.000000] LWS mult == 0 val == 70803c0 [ 0.000000] Generic PLL clk (983040000 Hz), parent (122880000 Hz),postdiv = 2, mult = 15, prediv = 0 [ 0.000000] LWS clock NAME refclk-ddr3a [ 0.000000] LWS mult == 0 val == 71803c0 [ 0.000000] Generic PLL clk (400000000 Hz), parent (100000000 Hz),postdiv = 4, mult = 15, prediv = 0 [ 0.000000] LWS clock NAME refclk-ddr3b [ 0.000000] LWS mult == 0 val == 98804c0 [ 0.000000] Generic PLL clk (1000000000 Hz), parent (100000000 Hz),postdiv = 2, mult = 19, prediv = 0 [ 0.000000] Architected local timer running at 200.00MHz (phys). REF CLOCK freq : pllctl0_val: MAIN_PLL :-122880000 => 3800901f ARM_PLL :- 125000000 => 17000bc4 DDR3A_PLL :- 100000000 => 71803c0 DDR3B_PLL :- 100000000 => 98804c0 PASS_PLL :- 122880000 => 70803c0 ____________________________________________________________________________________________________________________________________________________________________________________________________ REF CLOCK freq : MAIN_PLL :-122880000 => 38009c1f ARM_PLL :- 125000000 => 1b000dc4 DDR3A_PLL :- 100000000 => 71803c0 DDR3B_PLL :- 100000000 => 98804c0 PASS_PLL :- 122880000 => 70803c0 PDK kernel Prints :- MAIN_PLL [ 0.000000] LWS pllm 0 pllm_lower_mask 3f pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0 [ 0.000000] LWS clock name == armpllclk [ 0.000000] LWS read val 1b000dc4 [ 0.000000] LWS Generic PLL clk (1400000000 Hz), parent (125000000 Hz) postdiv = 1, mult = 55, prediv = 4 [ 0.000000] LWS pllm 0 pllm_lower_mask 3f pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7f000 [ 0.000000] LWS clock name == mainpllclk [ 0.000000] LWS read val 38009c1f [ 0.000000] LWS Main PLL clk (1200000000 Hz), parent (122880000 Hz) postdiv = 2, mult = 624, prediv = 31 [ 0.000000] LWS pllm 0 pllm_lower_mask 3f pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0 [ 0.000000] LWS clock name == papllclk [ 0.000000] LWS read val 70803c0 [ 0.000000] LWS Generic PLL clk (983040000 Hz), parent (122880000 Hz) postdiv = 2, mult = 15, prediv = 0 [ 0.000000] LWS pllm 0 pllm_lower_mask 3f pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0 [ 0.000000] LWS clock name == ddr3apllclk [ 0.000000] LWS read val 71803c0 [ 0.000000] LWS Generic PLL clk (400000000 Hz), parent (100000000 Hz) postdiv = 4, mult = 15, prediv = 0 [ 0.000000] LWS pllm 0 pllm_lower_mask 3f pllm_upper_shifti 6 plld_mask 3f pllm_upper_mask 7ffc0 [ 0.000000] LWS clock name == ddr3bpllclk [ 0.000000] LWS read val 98804c0 [ 0.000000] LWS Generic PLL clk (1000000000 Hz), parent (100000000 Hz) postdiv = 2, mult = 19, prediv = 0 _____________________________________________________________________________________________________________________________________________________________________________________________________