Sitara AM5718, Ethernet PHY loop back test (RMII link) Clock configuration from external 50MHz: @0x4a0093d0 set to 0x09000002 : CM_GMAC_GMAC_CLKCTRL[27:24]/CLKSEL_RFT/CLKSEL_REF, source of the GMAC_RFT_CLK: L3_ICLK, source of the RMII_50MHZ_CLK functional clock: GMAC_RMII_CLK ; [1:0]/ MODULEMODE, Module is explicitly enabled. @0x4a0093d0 set to 0x09000002 : CM_GMAC_GMAC_CLKCTRL[27:24]/CLKSEL_RFT/CLKSEL_REF, source of the GMAC_RFT_CLK: L3_ICLK, source of the RMII_50MHZ_CLK functional clock: GMAC_RMII_CLK ; [1:0]/ MODULEMODE, Module is explicitly enabled. @0x4A003C14 set to 0x00000100 : CTRL_CORE_SMA_SW_6: bit 8=0x100= enable 50MHz input clock for Ethernet Pin mux configuration for RMII1: @0x4A003650 set to 0x00050102 : ball W9, CTRL_CORE_PAD_RGMII0_TXC rmii1_rxd1 @0x4A003654 set to 0x00050102 : ball V9, CTRL_CORE_PAD_RGMII0_TXCTL rmii1_rxd0 @0x4A003670 set to 0x00030002 : ball V4, CTRL_CORE_PAD_RGMII0_RXD3 rmii1_txd0 @0x4A00366C set to 0x00010002 : ball V5, CTRL_CORE_PAD_RGMII0_RXCTL rmii1_txd1 @0x4A00364C set to 0x00050102 : ball Y1, CTRL_CORE_PAD_UART3_TXD rmii1_rxer @0x4A003648 set to 0x00050102 : ball V2, CTRL_CORE_PAD_UART3_RXD rmii1_crs @0x4A003668 set to 0x00050002 : ball U5, CTRL_CORE_PAD_RGMII0_RXC :rmii1_txen RMII mode selection: @0x4A002554 set to 0x3311 : CTRL_CORE_CONTROL_IO_1: RMII for RMII0 (port 1) and RMII1 (port 2= PHY) Clocks: @0x4A0093C0 set to 0x00000000 : CM_GMAC_CLKSTCTRL: CLKSEL_RFT=no sleep @0x4A0093D0 set to 0x09000002 : CM_GMAC_GMAC_CLKCTRL: Module is enabled with ext 50MHz clock @0x4A003644 set to 0x0004000F : CTRL_CORE_PAD_RMII_MHZ_50_CLK: 50MHz Sitara input on GPIO5_17, output off Apply Soft Reset to GMAC_SW Subsystem, CPSW_3G, CPGMAC_SL1/2, and CPDMA: @0x48484008 set to 0x00000001 : CPSW_SOFT_RESET - GMAC_SW 3G logic (INT, REGS, CPPI, and SPF modules) reset Wait @0x48484D8C set to 0x00000001 : SL_SOFT_RESET SL1 Wait @0x48484DCC set to 0x00000001 : SL_SOFT_RESET SL2 Wait @0x4848481C set to 0x00000000 : CPDMA_SOFT_RESET Wait @0x48485204 set to 0x00000001 : WR_SOFT_RESET Wait Initialize the HDPs (Header Description Pointer) and CPs (Completion Pointer) to NULL @0x48484A00--0x48484A7F set to 0x00000000 : Clear buffer descriptor pointer CPDMA_RX*/TX*_HDP and CPDMA_RX*/TX*_CP Interrupt setting: @0x4848488C set to 0x000000FF : CPDMA_TX_INTMASK_CLEAR: TX interrupts disabled @0x484848AC set to 0x0000FFFF : CPDMA_RX_INTMASK_CLEAR: TX interrupts disabled @0x484848BC set to 0x00000003 : CPDMA_DMA_INTMASK_CLEAR: interrupts disabled @0x48484888 set to 0x00000003 : CPDMA_INT TX interrupt mask set register: CPSW (=SS: Port 0=Sitara/1=VAHM_switch/2=PHY) switch setting: @0x48484004 set to 0x00000000 : CPSW_CONTROL (Switch control register) 0x0 as reset, no Fifo loopback @0x4848400C set to 0x00000007 : CPSW_STAT_PORT_EN: statistics enabled for Ports 0,1,2 @0x48484024 set to 0x00000007 : CPSW_FLOW_CONTROL: enable for Ports 0&1&2 Configure the ALE (Address Lookup Engine): (autorise addresses et multicast) @0x48484D08 set to 0x80000014 : (TBD: ok 0x80000014, KO 0x80000110) ALE_CONTROL: enable, bypass Address Lookup Engine, Flood if VLAN not found @0x48484D40 set to 0xFFFF0003 : ALE_PORTCTL0: port 0 forward @0x48484D44 set to 0xFFFF0003 : (TBD: ok 0xFFFF0000, KO 0xFFFF0003) ALE_PORTCTL1: port 1 forward @0x48484D48 set to 0xFFFF0003 : (TBD: ok 0xFFFF0000, KO 0xFFFF0003) ALE_PORTCTL2: port 2 forward (TBD: autoriser pour envoyer sur port 2? => FFFF0003) Configure the MDIO (already done) Configure the CPDMA: @0x48484804 set to 0x00000001 : Configure the CPDMA transmit DMA controller: Tx enable @0x48484814 set to 0x00000001 : Configure the CPDMA receive DMA controller: Tx enable @0x48484820 set to 0x00000010 : CPDMA DMACONTROL: RX error frames transferred Configure the CPPI TX and RX Descriptors ($24.11.4.11): @&RX_buffer_descriptor+0x0 set to 0x00000000 : Configure the CPPI RX Data word 0 : next descriptor pointer @&RX_buffer_descriptor+0x4 set to &RX_buffer : Configure the CPPI RX Data word 1 : buffer pointer @&RX_buffer_descriptor+0x8 set to 0x000001EF : Configure the CPPI RX Data word 2 : buffer offset, buffer length @&RX_buffer_descriptor+0xC set to 0x20020000 : Configure the CPPI RX Data word 3 : start, from port 2=RMII1 @&TX_buffer_descriptor+0x0 set to 0x00000000 : Configure the CPPI TX Data word 0 : next descriptor pointer @&TX_buffer_descriptor+0x4 set to &TX_buffer : Configure the CPPI TX Data word 1 : buffer pointer @&TX_buffer_descriptor+0x8 set to 0x00080130 : Configure the CPPI TX Data word 2 : buffer offset (+8 = skip preamble), buffer length (0x130 = wo preamble, with CRC) @&TX_buffer_descriptor+0xC set to 0xE4120130 : Configure the CPPI TX Data word 3 : packet start/end, CRC in packet, to port 2, length (0x130 with CRC) ... @0x01E23100 set to 0x51E02020 : MAC-RXMBPENABLE - Receive Multicast/Broadcast/Promiscuous Channel Enabled to Rx0 Configure sliver CPGMAC_SL1 and CPGMAC_SL2, as per the desired mode of operations @0x48484D84 set to 0x01E00039 : SL1_MACCONTROL - RMII, 10MB/s, Full duplex, no loopback @0x48484DC4 set to 0x01E00039 : SL2_MACCONTROL - RMII, 10MB/s, Full duplex, no loopback PORT setting: @0x48484100 set to 0x01300000 : CPSW_3GF PORT 0 control register (0x01300000: no priority, VLAN LTYPE 1&2 enabled) @0x48484200 set to 0x01300000 : CPSW_3GF PORT 1 control register (0x01000000: no priority) @0x48484300 set to 0x01300000 : CPSW_3GF PORT 2 control register (0x00000000: priority effect) @0x48484220 set to 0x000001FF : P1_SA_HI: port 1 MAC source address low @0x48484224 set to 0xECADEFBA : P1_SA_HI: port 1 MAC source address high @0x48484320 set to 0x000000FF : P2_SA_HI: port 2 MAC source address low @0x48484324 set to 0xECADEFBA : P2_SA_HI: port 2 MAC source address high SPF = Static Packet Filter: disabled CPTS = Time Sync : Disabled WR = wrapper (interruptions) @0x48485208 set to 0x00000005 : Wrapper, Subsystem control register: no idle Start up RX and TX DMA: @0x48484A20 set to &RX_buffer_descriptor : RX0_HDP - buffer descriptor pointer. Start up RX DMA (Write to HDP of RX) Wait @0x48484A00 set to &TX_buffer_descriptor : TX0_HDP - buffer descriptor pointer. Start up TX DMA (Write to HDP of TX) Wait ***************************************************************** Registers value after that is: CM_GMAC_CLKSTCTRL @0x4A0093C0 = 0x00001F00 => clock running, no idle => ok CM_GMAC_GMAC_CLKCTRL @0x4A0093D0 = 0x09000002 => enabled, GMAC_RMII_CLK (ext pin) used => ok CTRL_CORE_PAD_RMII_MHZ_50_CLK @0x4A003644 = 0x0005000F => input enable, Pull up, driver off CTRL_CORE_SMA_SW_6 @0x4A003C14 = 0x00000100 => ext clock from pin CTRL_CORE_CONTROL_IO_1 @0x4A002554 = 0x00003311 CPSW_SOFT_IDLE @0x48484014 = 0x00000000 PDMA_DMASTATUS @0x48484824 = 0x80000000 => idle SL1_MACSTATUS @0x48484D88 = 0x80000000 => idle SL2_MACSTATUS @0x48484DC8 = 0x80000000 => idle WR_STATUS @0x4848528C = 0x00000006 => SPF1&2 (Static Packet Filter) disabled. STATS GOOD_TX_FRAMES @0x48484934 = 0x00000000 => KO (all STATS registers are at 0) STATS TX_OCTETS @0x48484964 = 0x00000000 STATS GOOD_RX_FRAMES @0x48484900 = 0x00000000 TX0_CP @0x48484A40 = 0x48486000 => ok (CPDMA_STATERAM TX channel 0 completion pointer register updated TX0_HDP @0x48484A00 = 0x00000000 => ok (CPDMA_STATERAM TX channel 0 head descriptor pointer updated TX descriptor word 3 @0x4848600C = 0xD4120130 => ok, paquet envoyé (écrit 0xE4120130 => 0xF4120130 à tester?) RX0_CP @0x48484A60 = 0x00000000 => KO (CPDMA_STATERAM RX channel 0 completion pointer register) RX descriptor word 2 @0x48486008 = 0x000001EF RX descriptor word 3 @0x4848620C = 0x20020000