[18:23:19] TDA2xx SBL Boot 
[18:23:19]
[18:23:19] DPLL Configuration Completed 
[18:23:19]
[18:23:19] Clock Domain Configuration Completed 
[18:23:19]
[18:23:19] Module Enable Configuration Completed 
[18:23:19]
[18:23:19] TI EVM PAD Config Completed 
[18:23:19]ERROR: HW-Leveling time-out
[18:23:19]
[18:23:19] DDR Config Completed 
[18:23:19]
[18:23:19] App Image Download Begins 
[18:23:19]
[18:23:19] SD Boot - file open completed successfully 
[18:23:20]
[18:23:20] MPU CPU0 Image Load Completed 
[18:23:22]
[18:23:22] IPU1 CPU0 Image Load Completed 
[18:23:23]
[18:23:23] IPU1 CPU1 Image Load Completed 
[18:23:23]
[18:23:23] IPU2 CPU0 and CPU1 Image Load Completed 
[18:23:24]
[18:23:24] DSP1 Image Load Completed 
[18:23:25]
[18:23:25] DSP2 Image Load Completed 
[18:23:26]
[18:23:26] EVE1 Image Load Completed 
[18:23:26]
[18:23:26] EVE2 Image Load Completed 
[18:23:27]
[18:23:27] EVE3 Image Load Completed 
[18:23:27]
[18:23:27] EVE4 Image Load Completed 
[18:23:27]
[18:23:27] App Image Download Completed 
[18:23:27]
[18:23:27] Putting MPU CPU1 in Off mode 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27] EVE MMU configuration completed 
[18:23:27]
[18:23:27]*****************************************************************
[18:23:27]
[18:23:27] PMCCNTR counts once every 64 clock cycles, multiple by 64 to get actual CPU cycles 
[18:23:27]
[18:23:27] SBL Initial Config Cycles - 141597  (12.8 ms)
[18:23:27] SOC Init Cycles - 169272  (14.44 ms)
[18:23:27] DDR Config Clock Cycles - 99167  (8.46 ms)
[18:23:27] App Image Load Cycles - 92418524  (7886.38 ms)
[18:23:27] Slave Core Bootup Cycles - 208148  (17.76 ms)
[18:23:27] SBL Boot-up Cycles - 93037768  (7939.22 ms)
[18:23:27] Time at which SBL started IPU1_0 - 269191  (22.97 ms)
[18:23:27]*****************************************************************
[18:23:27]
[18:23:27] Jumping to MPU CPU0 App