C66xx_0: GEL Output: Connecting Target... C66xx_0: GEL Output: TCI6638K2K GEL file Ver is 1.60000002 C66xx_0: GEL Output: Detected PLL bypass disabled: SECCTL[BYPASS] = 0x00000000 C66xx_0: GEL Output: (3a) PLLCTL = 0x00000040 C66xx_0: GEL Output: (3b) PLLCTL = 0x00000040 C66xx_0: GEL Output: (3c) Delay... C66xx_0: GEL Output: (4)PLLM[PLLM] = 0x0000000F C66xx_0: GEL Output: MAINPLLCTL0 = 0x05000000 C66xx_0: GEL Output: (5) MAINPLLCTL0 = 0x07000000 C66xx_0: GEL Output: (5) MAINPLLCTL1 = 0x00000040 C66xx_0: GEL Output: (6) MAINPLLCTL0 = 0x07000000 C66xx_0: GEL Output: (7) SECCTL = 0x00090000 C66xx_0: GEL Output: (8a) Delay... C66xx_0: GEL Output: PLL1_DIV3 = 0x00008002 C66xx_0: GEL Output: PLL1_DIV4 = 0x00008004 C66xx_0: GEL Output: PLL1_DIV7 = 0x00000000 C66xx_0: GEL Output: (8d/e) Delay... C66xx_0: GEL Output: (10) Delay... C66xx_0: GEL Output: (12) Delay... C66xx_0: GEL Output: (13) SECCTL = 0x00090000 C66xx_0: GEL Output: (Delay... C66xx_0: GEL Output: (Delay... C66xx_0: GEL Output: (14) PLLCTL = 0x00000041 C66xx_0: GEL Output: PLL has been configured (CLKIN * PLLM / PLLD / PLLOD = PLLOUT): C66xx_0: GEL Output: PLL has been configured (122.879997 MHz * 16 / 1 / 2 = 983.039978 MHz) C66xx_0: GEL Output: Power on all PSC modules and DSP domains... C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=2, md=9! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=25! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=17, md=26! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=18, md=27! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=28! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=19, md=29! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=30! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=31! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=32! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=20, md=33! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=21, md=34! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=35! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=22, md=36! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=37! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=23, md=38! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=39! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=40! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=41! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=24, md=42! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=43! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=44! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=45! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=25, md=46! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=26, md=47! C66xx_0: GEL Output: Set_PSC_State... Timeout Error #03 pd=27, md=48! C66xx_0: GEL Output: Power on all PSC modules and DSP domains... Done. C66xx_0: GEL Output: WARNING: SYSCLK is the input to the PA PLL. C66xx_0: GEL Output: Completed PA PLL Setup C66xx_0: GEL Output: PAPLLCTL0 - before: 0x0x098804C0 after: 0x0x09080500 C66xx_0: GEL Output: PAPLLCTL1 - before: 0x0x00000040 after: 0x0x00002040 C66xx_0: GEL Output: DDR begin C66xx_0: GEL Output: XMC setup complete. C66xx_0: GEL Output: DDR3 PLL (PLL2) Setup ... C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3A clock now running at 666 MHz. C66xx_0: GEL Output: DDR3A initialization complete C66xx_0: GEL Output: DDR3 PLL Setup ... C66xx_0: GEL Output: DDR3 PLL Setup complete, DDR3B clock now running at 800MHz. C66xx_0: GEL Output: DDR3B initialization complete C66xx_0: GEL Output: DDR done