// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
/dts-v1/;
 
#include "am33xx.dtsi"
#include "am33xx-u-boot.dtsi"
/ {
    model = "TI AM335x BeagleTest";
    compatible = "ti,am335x-bone", "ti,am33xx";
    cpus {
            cpu@0 {
                cpu0-supply = <&vdd1_reg>;
            };
        };
 
        memory@80000000 {
            device_type = "memory";
            reg = <0x80000000 0x20000000>; /* 512 MB */
        };
 
        chosen {
            stdout-path = &uart0;
            tick-timer = &timer2;
        };
 
 
 
        vmmcsd_fixed: fixedregulator0 {
            compatible = "regulator-fixed";
            regulator-name = "vmmcsd_fixed";
            regulator-min-microvolt = <3300000>;
            regulator-max-microvolt = <3300000>;
        };
        vbat: fixedregulator1 {
            compatible = "regulator-fixed";
            regulator-name = "vbat";
            regulator-min-microvolt = <5000000>;
            regulator-max-microvolt = <5000000>;
            regulator-boot-on;
        };
};
 
 
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
*/
 
 
 
&am33xx_pinmux {
    pinctrl-names = "default";
    pinctrl-0 = <&clkout2_pin>;
 
    i2c0_pins: pinmux_i2c0_pins {
        pinctrl-single,pins = <
            AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT_PULLUP, MUX_MODE0)    /* i2c0_sda.i2c0_sda */
            AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT_PULLUP, MUX_MODE0)    /* i2c0_scl.i2c0_scl */
        >;
    };
 
    i2c2_pins: pinmux_i2c2_pins {
        pinctrl-single,pins = <
            AM33XX_PADCONF(AM335X_PIN_UART1_CTSN, PIN_INPUT_PULLUP, MUX_MODE3)  /* uart1_ctsn.i2c2_sda */
            AM33XX_PADCONF(AM335X_PIN_UART1_RTSN, PIN_INPUT_PULLUP, MUX_MODE3)  /* uart1_rtsn.i2c2_scl */
        >;
    };
    spi0_pins: pinmux_spi0_pins {
            pinctrl-single,pins = <
                AM33XX_PADCONF(0x950,PIN_INPUT_PULLDOWN,MUX_MODE0)  /* spi0_sclk.spi0_sclk*/
                AM33XX_PADCONF(0x954,PIN_INPUT_PULLUP,MUX_MODE0)    /* spi0_d0.spi0_d0 */
                AM33XX_PADCONF(0x958,PIN_INPUT_PULLDOWN,MUX_MODE0)  /* spi0_d1.spi0_d1 */               
                AM33XX_PADCONF(0x95c,PIN_INPUT_PULLUP,MUX_MODE0)    /* spi0_cs0.spi0_cs0 */         
                
                /* Interrupt from KZS8895 */
                AM33XX_PADCONF(0x92c,PIN_INPUT_PULLUP,MUX_MODE7)    /* mii1_tx_clk.gpio3_9 */
                
                /* Reset to KZS8895 */
                AM33XX_PADCONF(0x930,PIN_OUTPUT,MUX_MODE7)          /* mii1_rx_clk.gpio3_10 */
            >;
        };
 
    uart0_pins: pinmux_uart0_pins {
        pinctrl-single,pins = <
            AM33XX_PADCONF(AM335X_PIN_UART0_RXD, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_UART0_TXD, PIN_OUTPUT_PULLDOWN, MUX_MODE0)
        >;
    };
 
    clkout2_pin: pinmux_clkout2_pin {
        pinctrl-single,pins = <
            AM33XX_PADCONF(AM335X_PIN_XDMA_EVENT_INTR1, PIN_OUTPUT_PULLDOWN, MUX_MODE3) /* xdma_event_intr1.clkout2 */
        >;
    };
 
 
 
 
 
 
 
 
    mmc1_pins: pinmux_mmc1_pins {
        pinctrl-single,pins = <
            AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT, MUX_MODE7)      /* spio0_cs1.gpio0_6 */
            AM33XX_PADCONF(AM335X_PIN_MMC0_DAT0, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_MMC0_DAT1, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_MMC0_DAT2, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_MMC0_DAT3, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_MMC0_CMD, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_MMC0_CLK, PIN_INPUT_PULLUP, MUX_MODE0)
        >;
    };
    nandflash_pins_s0: nandflash_pins_s0 {
        pinctrl-single,pins = <
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_WPN, PIN_INPUT_PULLUP, MUX_MODE7)    /* gpmc_wpn.gpio0_31 */
            AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
            AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
        >;
    };
    mii2_pins: pinmux_mii2_pins {
        pinctrl-single,pins = <
            /* Slave 1 */
            AM33XX_PADCONF(0x840, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
            AM33XX_PADCONF(0x844, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
            AM33XX_PADCONF(0x848, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txd3.rgmii1_td3 */
            AM33XX_PADCONF(0x84c, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txd2.rgmii1_td2 */
            AM33XX_PADCONF(0x850, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txd1.rgmii1_td1 */
            AM33XX_PADCONF(0x854, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txd0.rgmii1_td0 */
            AM33XX_PADCONF(0x858, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txclk.rgmii1_tclk */
            AM33XX_PADCONF(0x85c, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxclk.rgmii1_rclk */
            AM33XX_PADCONF(0x860, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxd3.rgmii1_rd3 */
            AM33XX_PADCONF(0x864, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxd2.rgmii1_rd2 */
            AM33XX_PADCONF(0x868, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxd1.rgmii1_rd1 */
            AM33XX_PADCONF(0x86c, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxd0.rgmii1_rd0 */
        >;
    };
 
 
};
 
&uart0 {
    pinctrl-names = "default";
    pinctrl-0 = <&uart0_pins>;
 
    status = "okay";
};
 
&usb0 {
    dr_mode = "peripheral";
    interrupts-extended = <&intc 18 &tps 0>;
    interrupt-names = "mc", "vbus";
};
 
&usb1 {
    dr_mode = "host";
};
 
&i2c0 {
    pinctrl-names = "default";
    pinctrl-0 = <&i2c0_pins>;
 
    status = "okay";
    clock-frequency = <100000>;
 
    tps: tps@2D {
        reg = <0x2D>;
    };
 
    baseboard_eeprom: baseboard_eeprom@50 {
        compatible = "atmel,24c256";
        reg = <0x50>;
 
        #address-cells = <1>;
        #size-cells = <1>;
    };
};
 
&i2c2 {
    pinctrl-names = "default";
    pinctrl-0 = <&i2c2_pins>;
 
    status = "okay";
    clock-frequency = <100000>;
 
    cape_eeprom0: cape_eeprom0@54 {
        compatible = "atmel,24c256";
        reg = <0x54>;
        #address-cells = <1>;
        #size-cells = <1>;
        cape0_data: cape_data@0 {
            reg = <0 0x100>;
        };
    };
 
    cape_eeprom1: cape_eeprom1@55 {
        compatible = "atmel,24c256";
        reg = <0x55>;
        #address-cells = <1>;
        #size-cells = <1>;
        cape1_data: cape_data@0 {
            reg = <0 0x100>;
        };
    };
 
    cape_eeprom2: cape_eeprom2@56 {
        compatible = "atmel,24c256";
        reg = <0x56>;
        #address-cells = <1>;
        #size-cells = <1>;
        cape2_data: cape_data@0 {
            reg = <0 0x100>;
        };
    };
 
    cape_eeprom3: cape_eeprom3@57 {
        compatible = "atmel,24c256";
        reg = <0x57>;
        #address-cells = <1>;
        #size-cells = <1>;
        cape3_data: cape_data@0 {
            reg = <0 0x100>;
        };
    };
};
&spi0 {
            status = "okay";
            pinctrl-names = "default";
            pinctrl-0 = <&spi0_pins>;
            ti,pindir-d0-out-d1-in = <1>;
            
 
            ksz8895: ksz8895@0 {
                compatible = "microchip,ksz8895";
                status = "okay";
                spi-max-frequency = <12000000>;       
                spi-cpha;
                spi-cpol;          
                reg = <0>;  /* Chip select 0 */
                
                ksz8895,gpio_reset = <106>; /* GPIO_TO_PIN(3,10) */
                ksz8895,gpio_irq = <105>; /* GPIO_TO_PIN(3,9) */
                ports {
                        #address-cells = <1>;
                        #size-cells = <0>;
                        port@0 {
                            reg = <0>;
                            label = "lan1";
                        };
                        port@1 {
                            reg = <1>;
                            label = "lan2";
                        };
                        port@2 {
                            reg = <2>;
                            label = "lan3";
                        };
                        port@3 {
                            reg = <3>;
                            label = "lan4";
                        };
                        port@4 {
                            reg = <4>;
                            label = "cpu";
                            ethernet = <&mac>;
                            phy-mode = "mii";
                            fixed-link {
                                speed = <100>;
                                full-duplex;
                                pause;
                            };
                        };
                    };
            };
        };
&elm{
            status = "okay";
        };
&gpmc {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&nandflash_pins_s0>;
    ranges = <0 0 0x08000000 0x1000000>;    /* CS0: 16MB for NAND */
    nand@0,0 {
        reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
        ti,nand-ecc-opt = "bch8";
        ti,elm-id = <&elm>;
        nand-bus-width = <8>;
        gpmc,device-width = <1>;
        gpmc,sync-clk-ps = <0>;
        gpmc,cs-on-ns = <0>;
        gpmc,cs-rd-off-ns = <44>;
        gpmc,cs-wr-off-ns = <44>;
        gpmc,adv-on-ns = <6>;
        gpmc,adv-rd-off-ns = <34>;
        gpmc,adv-wr-off-ns = <44>;
        gpmc,we-on-ns = <0>;
        gpmc,we-off-ns = <40>;
        gpmc,oe-on-ns = <0>;
        gpmc,oe-off-ns = <54>;
        gpmc,access-ns = <64>;
        gpmc,rd-cycle-ns = <82>;
        gpmc,wr-cycle-ns = <82>;
        gpmc,wait-on-read = "true";
        gpmc,wait-on-write = "true";
        gpmc,bus-turnaround-ns = <0>;
        gpmc,cycle2cycle-delay-ns = <0>;
        gpmc,clk-activation-ns = <0>;
        gpmc,wait-monitoring-ns = <0>;
        gpmc,wr-access-ns = <40>;
        gpmc,wr-data-mux-bus-ns = <0>;
        /* MTD partition table */
        /* All SPL-* partitions are sized to minimal length
         * which can be independently programmable. For
         * NAND flash this is equal to size of erase-block */
        #address-cells = <1>;
        #size-cells = <1>;
        partition@0 {
            label = "NAND.SPL";
            reg = <0x00000000 0x00020000>;
        };
        partition@1 {
            label = "NAND.SPL.backup1";
            reg = <0x00020000 0x00020000>;
        };
        partition@2 {
            label = "NAND.SPL.backup2";
            reg = <0x00040000 0x00020000>;
        };
        partition@3 {
            label = "NAND.SPL.backup3";
            reg = <0x00060000 0x00020000>;
        };
        partition@4 {
            label = "NAND.u-boot-spl-os";
            reg = <0x00080000 0x00040000>;
        };
        partition@5 {
            label = "NAND.u-boot";
            reg = <0x000C0000 0x00100000>;
        };
        partition@6 {
            label = "NAND.u-boot-env";
            reg = <0x001C0000 0x00020000>;
        };
        partition@7 {
            label = "NAND.u-boot-env.backup1";
            reg = <0x001E0000 0x00020000>;
        };
        partition@8 {
            label = "NAND.kernel";
            reg = <0x00200000 0x00800000>;
        };
        partition@9 {
            label = "NAND.file-system";
            reg = <0x00A00000 0x0F600000>;
        };
    };
};
 
/include/ "tps65910.dtsi"
 
&tps {
    ti,en-ck32k-xtal = "true";
    
    vcc1-supply = <&vbat>;
    vcc2-supply = <&vbat>;
    vcc3-supply = <&vbat>;
    vcc4-supply = <&vbat>;
    vcc5-supply = <&vbat>;
    vcc6-supply = <&vbat>;
    vcc7-supply = <&vbat>;
    vccio-supply = <&vbat>;
 
    regulators {
        vrtc_reg: regulator@0 {
            regulator-always-on;
        };
 
        vio_reg: regulator@1 {
            regulator-always-on;
        };
 
        vdd1_reg: regulator@2 {
            /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */
            regulator-name = "vdd_mpu";
            regulator-min-microvolt = <912500>;
            regulator-max-microvolt = <1312500>;
            regulator-boot-on;
            regulator-always-on;
        };
 
        vdd2_reg: regulator@3 {
            /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
            regulator-name = "vdd_core";
            regulator-min-microvolt = <912500>;
            regulator-max-microvolt = <1150000>;
            regulator-boot-on;
            regulator-always-on;
        };
 
        vdd3_reg: regulator@4 {
            regulator-always-on;
        };
 
        vdig1_reg: regulator@5 {
            regulator-always-on;
        };
 
        vdig2_reg: regulator@6 {
            regulator-always-on;
        };
 
        vpll_reg: regulator@7 {
            regulator-always-on;
        };
 
        vdac_reg: regulator@8 {
            regulator-always-on;
        };
 
        vaux1_reg: regulator@9 {
            regulator-always-on;
        };
 
        vaux2_reg: regulator@10 {
            regulator-always-on;
        };
 
        vaux33_reg: regulator@11 {
            regulator-always-on;
        };
    };
};
 
 
 
 
 
&mac {
    status = "okay";
    pinctrl-names = "default";
    pinctrl-0 = <&mii2_pins>;
    dual_emac = <1>;
};

&cpsw_emac0 {
    status = "okay";
    phy_id      = "0:00";
    dual_emac_res_vlan = <2>;       
};
 
&cpsw_emac1 {
    status = "okay";
    phy_id      = "0:01";
    dual_emac_res_vlan = <3>;           
};
 
 
 
&mmc1 {
    status = "okay";
    bus-width = <0x4>;
    pinctrl-names = "default";
    pinctrl-0 = <&mmc1_pins>;
    cd-gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
};
 
&aes {
    status = "okay";
};
 
&sham {
    status = "okay";
};
 
&rtc {
    status = "disabled";
};