/*
 * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
/dts-v1/;

#include "dra72x.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-idk-common.dtsi"
#include "dra72x-mmc-iodelay.dtsi"

/ {
	model = "TI AM5718 IDK";
	compatible = "ti,am5718-idk", "ti,am5718", "ti,dra7";

	memory@80000000 {
		device_type = "memory";
		reg = <0x0 0x80000000 0x0 0x40000000>;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu2_cma_pool: ipu2_cma@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		dsp1_cma_pool: dsp1_cma@99000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x99000000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu1_cma_pool: ipu1_cma@9d000000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9d000000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};
	};

	/* Dual mac ethernet application node on icss2 */
	pruss1_eth: pruss1_eth {
		status = "okay";
		compatible = "ti,am57-prueth";
		pruss = <&pruss1>;
		sram = <&ocmcram1>;
		interrupt-parent = <&pruss1_intc>;

		pruss1_emac0: ethernet-mii0 {
			phy-handle = <&pruss1_eth0_phy>;
			phy-mode = "mii";
			interrupts = <20>, <22>, <23>;
			interrupt-names = "rx", "tx", "ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};

		pruss1_emac1: ethernet-mii1 {
			phy-handle = <&pruss1_eth1_phy>;
			phy-mode = "mii";
			interrupts = <21>, <23>, <24>;
			interrupt-names = "rx", "tx", "ptp_tx";
			/* Filled in by bootloader */
			local-mac-address = [00 00 00 00 00 00];
		};
	};
};

&mmc1 {
	pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104";
	pinctrl-0 = <&mmc1_pins_default>;
	pinctrl-1 = <&mmc1_pins_hs>;
	pinctrl-2 = <&mmc1_pins_sdr12>;
	pinctrl-3 = <&mmc1_pins_sdr25>;
	pinctrl-4 = <&mmc1_pins_sdr50>;
	pinctrl-5 = <&mmc1_pins_ddr50_rev20 &mmc1_iodelay_ddr50_conf>;
	pinctrl-6 = <&mmc1_pins_sdr104 &mmc1_iodelay_sdr104_rev20_conf>;
};

&mmc2 {
	pinctrl-names = "default", "hs", "ddr_1_8v";
	pinctrl-0 = <&mmc2_pins_default>;
	pinctrl-1 = <&mmc2_pins_hs>;
	pinctrl-2 = <&mmc2_pins_ddr_rev20 &mmc2_iodelay_ddr_conf>;
};

&omap_dwc3_1 {
	extcon = <&extcon_usb2>;
};

&extcon_usb2 {
	id-gpio = <&gpio5 7 GPIO_ACTIVE_HIGH>;
	vbus-gpio = <&gpio7 22 GPIO_ACTIVE_HIGH>;
};

&cpu0 {
	vdd-supply = <&smps12_reg>;
};

&ov2659_1 {
	remote-endpoint = <&vin1b>;
};

&vin1b {
	status = "okay";

	endpoint@2 {
		slave-mode;
		remote-endpoint = <&ov2659_1>;
	};
};

&vip1 {
	status = "okay";
};

&mailbox5 {
	status = "okay";
	mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
		status = "disable";
	};
	mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
		status = "disable";
	};
};

&mailbox6 {
	status = "okay";
	mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
		status = "disable";
	};
};

&mmu0_dsp1 {
	status = "okay";
};

&mmu1_dsp1 {
	status = "okay";
};

&mmu_ipu1 {
	status = "okay";
};

&mmu_ipu2 {
	status = "okay";
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_cma_pool>;
	mboxes = <&mailbox6 &mbox_ipu2_ipc3x>;
	timers = <&timer3>;
	watchdog-timers = <&timer4>, <&timer9>;
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_cma_pool>;
	mboxes = <&mailbox5 &mbox_ipu1_ipc3x>;
	timers = <&timer11>;
	watchdog-timers = <&timer7>, <&timer8>;
};

&dsp1 {
	status = "disabled";
	memory-region = <&dsp1_cma_pool>;
	mboxes = <&mailbox5 &mbox_dsp1_ipc3x>;
	timers = <&timer5>;
	watchdog-timers = <&timer10>;
};

&pcie1_rc {
	status = "disabled";
	gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
};

&pcie1_ep {
	/*
	 * To enable PCIe EP functionality, set the status of
	 * this node to "okay" and the status of pcie1_rc node
	 * above to "disabled".
	 */
	status = "disabled";
	gpios = <&gpio5 18 GPIO_ACTIVE_HIGH>;
};

&pruss1_mdio {
	status = "disable";
	reset-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
	pruss1_eth0_phy: ethernet-phy@0 {
		reg = <0>;
		interrupt-parent = <&gpio3>;
		interrupts = <28 IRQ_TYPE_EDGE_FALLING>;
	};

	pruss1_eth1_phy: ethernet-phy@1 {
		reg = <1>;
		interrupt-parent = <&gpio3>;
		interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
	};
};

&pruss2_mdio {
	reset-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>;
	reset-delay-us = <2>;   /* PHY datasheet states 1uS min */
};

&pru1_1 {
	ti,pruss-gp-mux-sel = <4>;	/* MII2, needed for PRUSS1_MII1 */
};

&pru2_0 {
	ti,pruss-gp-mux-sel = <4>;	/* MII2, needed for PRUSS1_MII0 */
};

&pru2_1 {
	ti,pruss-gp-mux-sel = <4>;	/* MII2, needed for PRUSS1_MII1 */
};

&qspi {
	spi-max-frequency = <76800000>;
	m25p80@0 {
		spi-max-frequency = <76800000>;
	};
};



&pwm5 {
		status = "okay";		
};
&pwm6 {
		status = "okay";		
};
&pwm7 {
		status = "okay";		
};
&pwm8 {
		status = "okay";		
};
&pwm9 {
		status = "okay";		
};
&pwm10 {
		status = "okay";
};
&pwm11 {
		status = "okay";
};
&pwm12 {
		status = "okay";		
};


&mcspi1 {
        status = "okay";
        ti,pindir-d0-out-d1-in;

        spidev@0{
                  compatible = "linux,spidev";
                  spi-max-frequency = <12000000>;
                  reg = <0x0>;
                  status = "okay";
        };
        
};

&mcspi3 {
        status = "okay";
        ti,pindir-d0-in-d1-out;

        spidev@0{
				
		  compatible = "linux,spidev";
                  spi-max-frequency = <12000000>;
                  reg = <0x0>;
                  status = "okay";
        };
       

};

#include "am57xx-evm-cmem-am571x.dtsi"

#include "am57xx-evm-cmem-am571x.dtsi"

#include "am57xx-evm-cmem-am571x.dtsi"