/*
 * Copyright (C) 2018 PHYTEC America, LLC. - https://www.phytec.com
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include "am57xx-commercial-grade.dtsi"

/ {
	aliases {
		rtc0 = &rtc;
		rtc1 = &tps659038_rtc;
	};

	reserved-memory {
		#address-cells = <2>;
		#size-cells = <2>;
		ranges;

		ipu1_memory_region: ipu1-memory@95800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x95800000 0x0 0x2000000>;
			reusable;
			status = "okay";
		};

		dsp1_memory_region: dsp1-memory@97800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x97800000 0x0 0x4000000>;
			reusable;
			status = "okay";
		};

		ipu2_memory_region: ipu2-memory@9b800000 {
			compatible = "shared-dma-pool";
			reg = <0x0 0x9b800000 0x0 0x3800000>;
			reusable;
			status = "okay";
		};

		cmem_block_mem_0: cmem_block_mem@a0000000 {
			reg = <0x0 0xa0000000 0x0 0x0c000000>;
			no-map;
			status = "okay";
		};
	};

	cmem {
		compatible = "ti,cmem";
		#address-cells = <1>;
		#size-cells = <0>;

		#pool-size-cells = <2>;

		status = "okay";

		cmem_block_0: cmem_block@0 {
			reg = <0>;
			memory-region = <&cmem_block_mem_0>;
			cmem-buf-pools = <1 0x0 0x0c000000>;
		};
	};

	vdd_3v3: fixedregulator-vdd_3v3 {
		compatible = "regulator-fixed";
		regulator-name = "vdd_3v3";
		vin-supply = <&regen1>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
	};

	aic_dvdd: fixedregulator-aic_dvdd {
		compatible = "regulator-fixed";
		regulator-name = "aic_dvdd_fixed";
		vin-supply = <&vdd_3v3>;
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <1800000>;
	};

	vtt_fixed: fixedregulator-vtt {
		/* TPS51200 */
		compatible = "regulator-fixed";
		regulator-name = "vtt_fixed";
		vin-supply = <&smps3_reg>;
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-always-on;
		regulator-boot-on;
		enable-active-high;
		gpio = <&gpio4 8 GPIO_ACTIVE_HIGH>;
	};

	phytec_leds: leds {
		compatible = "gpio-leds";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&leds_som_pins_default>;
		pinctrl-1 = <&leds_som_pins_sleep>;

		led@0 {
			label = "am57xx-phycore-som:red";
			gpios = <&gpio4 9 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "heartbeat";
			default-state = "off";
		};

		led@1 {
			label = "am57xx-phycore-som:green";
			gpios = <&gpio4 10 GPIO_ACTIVE_HIGH>;
			linux,default-trigger = "cpu0";
			default-state = "off";
		};
	};
};

&dra7_pmx_core {
	leds_som_pins_default: leds_som_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3588, PIN_OUTPUT | MUX_MODE14)	/* (F5) vin2a_d8.gpio4_9 */
			DRA7XX_CORE_IOPAD(0x358c, PIN_OUTPUT | MUX_MODE14)	/* (E6) vin2a_d9.gpio4_10 */
		>;
	};

	leds_som_pins_sleep: leds_som_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3588, PIN_INPUT_PULLDOWN | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x358c, PIN_INPUT_PULLDOWN | MUX_MODE15)
		>;
	};

	i2c1_pins_default: i2c1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT_PULLUP | MUX_MODE0)	/* (C21) i2c1_sda */
			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT_PULLUP | MUX_MODE0)	/* (C20) i2c1_scl */
		>;
	};

	i2c1_pins_sleep: i2c1_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3800, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3804, PIN_INPUT | MUX_MODE15)
		>;
	};

	mmc2_pins_sleep: mmc2_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x349c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34b0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34a0, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34a4, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34a8, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x34ac, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x348c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3490, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3494, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3498, PIN_INPUT | MUX_MODE15)
		>;
	};

	emac0_pins_default: emac0_pins_default {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3650, PIN_OUTPUT | MUX_MODE0)	/* (W9) rgmii0_txc */
			DRA7XX_CORE_IOPAD(0x3654, PIN_OUTPUT | MUX_MODE0)	/* (V9) rgmii0_txctl */
			DRA7XX_CORE_IOPAD(0x3658, PIN_OUTPUT | MUX_MODE0)	/* (V7) rgmii0_txd3 */
			DRA7XX_CORE_IOPAD(0x365c, PIN_OUTPUT | MUX_MODE0)	/* (U7) rgmii0_txd2 */
			DRA7XX_CORE_IOPAD(0x3660, PIN_OUTPUT | MUX_MODE0)	/* (V6) rgmii0_txd1 */
			DRA7XX_CORE_IOPAD(0x3664, PIN_OUTPUT | MUX_MODE0)	/* (U6) rgmii0_txd0 */
			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE0)	/* (U5) rgmii0_rxc */
			DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE0)	/* (V5) rgmii0_rxctl */
			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE0)	/* (V4) rgmii0_rxd3 */
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE0)	/* (V3) rgmii0_rxd2 */
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE0)	/* (Y2) rgmii0_rxd1 */
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE0)	/* (W2) rgmii0_rxd0 */
		>;

	};

	emac0_pins_sleep: emac0_pins_sleep {
		pinctrl-single,pins = <
			/* Slave 1 */
			DRA7XX_CORE_IOPAD(0x3650, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3654, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3658, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x365c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3660, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3664, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3668, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x366c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3670, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3674, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3678, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x367c, PIN_INPUT | MUX_MODE15)
		>;
	};

	davinci_mdio_pins_default: davinci_mdio_pins_default {
		pinctrl-single,pins = <
			/* MDIO */
			DRA7XX_CORE_IOPAD(0x363c, PIN_OUTPUT_PULLUP | MUX_MODE0)	/* (V1) mdio_mclk */
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT_PULLUP | MUX_MODE0)		/* (U4) mdio_d */
		>;
	};

	davinci_mdio_pins_sleep: davinci_mdio_pins_sleep {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x363c, PIN_INPUT | MUX_MODE15)
			DRA7XX_CORE_IOPAD(0x3640, PIN_INPUT | MUX_MODE15)
		>;
	};

	tps659038_pins_default: tps659038_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3818, PIN_INPUT_PULLUP | MUX_MODE14)	/* (AD17) Wakeup0.gpio1_0 */
		>;
	};

	mcspi1_pins_default: mcspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x37a4, PIN_INPUT | MUX_MODE0)         /* spi1_sclk */
			DRA7XX_CORE_IOPAD(0x37a8, PIN_INPUT | MUX_MODE0)         /* spi1_d1 */
			DRA7XX_CORE_IOPAD(0x37ac, PIN_INPUT | MUX_MODE0)         /* spi1_d0 */
			DRA7XX_CORE_IOPAD(0x37b0, PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi1_cs0 */
			DRA7XX_CORE_IOPAD(0x37b4, PIN_OUTPUT_PULLUP | MUX_MODE0) /* spi1_cs1 */
		>;
	};

	qspi1_pins_default: qspi1_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3474, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (R3) gpmc_a13.qspi1_rtclk */
			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (T2) gpmc_a14.qspi1_d3 */
			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (U2) gpmc_a15.qspi1_d2 */
			DRA7XX_CORE_IOPAD(0x3480, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (U1) gpmc_a16.qspi1_d0 */
			DRA7XX_CORE_IOPAD(0x3484, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (P3) gpmc_a17.qspi1_d1 */
			DRA7XX_CORE_IOPAD(0x3488, PIN_INPUT | MODE_SELECT | MUX_MODE1)	/* (R2) gpmc_a18.qspi1_sclk */
		>;
	};

	qspi1_legacy_pins: qspi1_legacy_pins {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3478, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1)	/* (T2) gpmc_a14.qspi1_d3 */
			DRA7XX_CORE_IOPAD(0x347c, PIN_INPUT_PULLUP | MODE_SELECT | MUX_MODE1)	/* (U2) gpmc_a15.qspi1_d2 */
		>;
	};

	qspi1_cs0_pin: qspi1_cs0_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34b8, PIN_OUTPUT | MODE_SELECT | MUX_MODE1)	/* (P2) gpmc_cs2.qspi1_cs0 */
		>;
	};

	qspi1_cs1_pin: qspi1_cs1_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x34bc, PIN_OUTPUT | MODE_SELECT | MUX_MODE1)	/* (P1) gpmc_cs3.qspi1_cs1 */
		>;
	};

	qspi1_cs2_pin: qspi1_cs2_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x344c, PIN_OUTPUT | MODE_SELECT | MUX_MODE1)	/* (T7) gpmc_a3.qspi1_cs2 */
		>;
	};

	gpmc_nand_pins_default: gpmc_nand_pins_default {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3400, PIN_INPUT_SLEW | MUX_MODE0)			/* (M6) gpmc_ad0 */
			DRA7XX_CORE_IOPAD(0x3404, PIN_INPUT_SLEW | MUX_MODE0)			/* (M2) gpmc_ad1 */
			DRA7XX_CORE_IOPAD(0x3408, PIN_INPUT_SLEW | MUX_MODE0)			/* (L5) gpmc_ad2 */
			DRA7XX_CORE_IOPAD(0x340c, PIN_INPUT_SLEW | MUX_MODE0)			/* (M1) gpmc_ad3 */
			DRA7XX_CORE_IOPAD(0x3410, PIN_INPUT_SLEW | MUX_MODE0)			/* (L6) gpmc_ad4 */
			DRA7XX_CORE_IOPAD(0x3414, PIN_INPUT_SLEW | MUX_MODE0)			/* (L4) gpmc_ad5 */
			DRA7XX_CORE_IOPAD(0x3418, PIN_INPUT_SLEW | MUX_MODE0)			/* (L3) gpmc_ad6 */
			DRA7XX_CORE_IOPAD(0x341c, PIN_INPUT_SLEW | MUX_MODE0)			/* (L2) gpmc_ad7 */
			DRA7XX_CORE_IOPAD(0x34b4, PIN_OUTPUT_PULLUP | SLEWCONTROL | MUX_MODE0)	/* (T1) gpmc_cs0 */
			DRA7XX_CORE_IOPAD(0x34c4, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (N1) gpmc_advn_ale */
			DRA7XX_CORE_IOPAD(0x34c8, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (M5) gpmc_oen_ren */
			DRA7XX_CORE_IOPAD(0x34cc, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (M3) gpmc_wen */
			DRA7XX_CORE_IOPAD(0x34d0, PIN_OUTPUT | SLEWCONTROL | MUX_MODE0)		/* (N6) gpmc_ben0 */
			DRA7XX_CORE_IOPAD(0x34d8, PIN_INPUT_SLEW | MUX_MODE14)			/* (N2) gpmc_wait0.gpio2_28 */
			DRA7XX_CORE_IOPAD(0x356c, PIN_INPUT_PULLUP | MUX_MODE15)		/* (F3) vin2a_d1.off */
		>;
	};

	eeprom_wp_pin: eeprom_wp_pin {
		pinctrl-single,pins = <
			DRA7XX_CORE_IOPAD(0x3724, PIN_OUTPUT | MUX_MODE14)	/* mcasp3_aclkx.gpio5_13 */
		>;
	};
};

&dra7_iodelay_core {
	qspi1_iodelay_conf: qspi1_iodelay_conf {
		pinctrl-pin-array = <
			0x144 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A13_IN */
			0x150 A_DELAY_PS(2575) G_DELAY_PS(966)	/* CFG_GPMC_A14_IN */
			0x15c A_DELAY_PS(2503) G_DELAY_PS(889)	/* CFG_GPMC_A15_IN */
			0x168 A_DELAY_PS(2528) G_DELAY_PS(1007)	/* CFG_GPMC_A16_IN */
			0x170 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_A16_OUT */
			0x174 A_DELAY_PS(2533) G_DELAY_PS(980)	/* CFG_GPMC_A17_IN */
			0x188 A_DELAY_PS(590) G_DELAY_PS(0)	/* CFG_GPMC_A18_OUT */
			0x218 A_DELAY_PS(114) G_DELAY_PS(0)	/* CFG_GPMC_A3_OUT */
			0x374 A_DELAY_PS(0) G_DELAY_PS(0)	/* CFG_GPMC_CS2_OUT */
			0x380 A_DELAY_PS(70) G_DELAY_PS(0)	/* CFG_GPMC_CS3_OUT */
		>;
	};
};

&i2c1 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&i2c1_pins_default>;
	pinctrl-1 = <&i2c1_pins_sleep>;
	clock-frequency = <400000>;

	tps659038: tps659038@58 {
		compatible = "ti,tps659038";
		reg = <0x58>;

		pinctrl-names = "default";
		pinctrl-0 = <&tps659038_pins_default>;

		interrupt-parent = <&gpio1>;
		interrupts = <0 IRQ_TYPE_LEVEL_LOW>;

		#interrupt-cells = <2>;
		interrupt-controller;

		ti,system-power-controller;
		ti,palmas-override-powerhold;

		tps659038_pmic {
			compatible = "ti,tps659038-pmic";

			smps12-in-supply = <&vcc_3v3>;
			smps3-in-supply = <&vcc_3v3>;
			smps45-in-supply = <&vcc_3v3>;
			smps6-in-supply = <&vcc_3v3>;
			smps8-in-supply = <&vcc_3v3>;
			ldo1-in-supply = <&vcc_5v0>;
			ldo2-in-supply = <&vcc_5v0>;
			ldo3-in-supply = <&vcc_3v3>;
			ldo4-in-supply = <&vcc_3v3>;
			ldo9-in-supply = <&vcc_3v3>;
			ldoln-in-supply = <&vcc_3v3>;
			ldousb-in-supply = <&vcc_5v0>;

			regulators {
				smps12_reg: smps12 {
					/* VDD_MPU */
					regulator-name = "smps12";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1250000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps3_reg: smps3 {
					/* VDD_DDR */
					regulator-name = "smps3";
					regulator-min-microvolt = <1350000>;
					regulator-max-microvolt = <1350000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps45_reg: smps45 {
					/* VDD_DSPEVE, VDD_IVA, VDD_GPU */
					regulator-name = "smps45";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1150000>;
					regulator-always-on;
					regulator-boot-on;
				};

				smps6_reg: smps6 {
					/* VDD_CORE */
					regulator-name = "smps6";
					regulator-min-microvolt = <850000>;
					regulator-max-microvolt = <1030000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* SMPS7 unused */

				smps8_reg: smps8 {
					/* VDD_1V8 */
					regulator-name = "smps8";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				/* SMPS9 unused */

				ldo1_reg: ldo1 {
					/* VDD_SD / VDDSHV8  */
					regulator-name = "ldo1";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo2_reg: ldo2 {
					/* VDD_SHV5 */
					regulator-name = "ldo2";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo3_reg: ldo3 {
					/* VDDA_1V8_PHYA */
					regulator-name = "ldo3";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo4_reg: ldo4 {
					/* VDDA_1V8_PHYB */
					regulator-name = "ldo4";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldo9_reg: ldo9 {
					/* VDD_RTC */
					regulator-name = "ldo9";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldoln_reg: ldoln {
					/* VDDA_1V8_PLL */
					regulator-name = "ldoln";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
					regulator-boot-on;
				};

				ldousb_reg: ldousb {
					/* VDDA_3V_USB: VDDA_USBHS33 */
					regulator-name = "ldousb";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-boot-on;
				};

				regen1: regen1 {
					/* VDD_3V3_ON */
					regulator-name = "regen1";
					regulator-boot-on;
					regulator-always-on;
				};
			};
		};

		tps659038_pwr_button: tps659038_pwr_button {
			compatible = "ti,palmas-pwrbutton";
			interrupt-parent = <&tps659038>;
			interrupts = <1 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
			ti,palmas-long-press-seconds = <12>;
		};

		tps659038_rtc: tps659038_rtc {
			status = "okay";
			compatible = "ti,palmas-rtc";
			interrupt-parent = <&tps659038>;
			interrupts = <8 IRQ_TYPE_EDGE_FALLING>;
			wakeup-source;
		};
	};

	i2c_eeprom: eeprom@50 {
		status = "okay";
		compatible = "atmel,24c32";
		pinctrl-names = "default";
		pinctrl-0 = <&eeprom_wp_pin>;
		wp-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>;
		reg = <0x50>;
		pagesize = <32>;
	};

	i2c_rtc: rtc@68 {
		status = "disabled";
		compatible = "microcrystal,rv4162";
		reg = <0x68>;
	};
};

&gpio4 {
	ti,no-reset-on-init;
	ti,no-idle-on-init;
};

&mcasp1 {
	compatible = "ti,dra7-mcasp1-audio";
	reg = <0x48460000 0x2000>,
	      <0x45800000 0x400000>;
	reg-names = "mpu", "dat";
};

&mac {
	status = "okay";
	slaves = <1>;
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&emac0_pins_default>;
	pinctrl-1 = <&emac0_pins_sleep>;
};

&davinci_mdio {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&davinci_mdio_pins_default>;
	pinctrl-1 = <&davinci_mdio_pins_sleep>;

	phy0: ethernet-phy@1 {
		reg = <1>;
	};
};

&cpsw_emac0 {
	status = "okay";

	phy-handle = <&phy0>;
	phy-mode = "rgmii";
	dual_emac_res_vlan = <1>;
};

&cpsw_emac1 {
	status = "okay";
};

&mmc2 {
	status = "okay";
	vmmc-supply = <&vdd_3v3>;
	vqmmc-supply = <&vdd_3v3>;
	bus-width = <8>;
	non-removable;
	max-frequency = <96000000>;
	no-1-8-v;
};

&mcspi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcspi1_pins_default>;

	ti,pindir-d0-out-d1-in;
};

/* NOTE: support added for pcie2 in endpoint mode
 *       additionally, setting axi1 { status = "okay" };
 *       is necessary for any pcie2 use.
 *
 *       pcie2_rc/ep are incompatible with PCM-948
 */
&axi1 {
	pcie2_ep: pcie_ep@51800000 {
		compatible = "ti,dra7-pcie-ep";
		reg = <0x51800000 0x28>, <0x51802000 0x14c>,
		      <0x51801000 0x28>, <0x1000 0x10000000>;
		reg-names = "ep_dbics", "ti_conf", "ep_dbics2", "addr_space";
		interrupts = <0 355 0x4>;
		num-lanes = <1>;
		num-ib-windows = <4>;
		num-ob-windows = <16>;
		ti,hwmods = "pcie2";
		phys = <&pcie2_phy>;
		phy-names = "pcie-phy1";
		syscon-legacy-mode = <&scm_conf1 0x14 1>;
		status = "okay";
	};
};

&qspi {
	status = "okay";

	pinctrl-names = "default";
	pinctrl-0 = <&qspi1_pins_default &qspi1_iodelay_conf>;

	spi-max-frequency = <76800000>;

	/* .3 and older PCB has QSPI NOR populated on
	 * CS2, cannot support more than SPI-DIO mode,
	 * and requires internal pull-ups on D2/D3
	 */
	qspi_nor: m25p80@2 {
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&qspi1_legacy_pins &qspi1_cs2_pin>;
		compatible = "n25q128a13", "jedec,spi-nor";

		reg = <2>;
		spi-max-frequency = <76800000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <2>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000040000>;
		};
		partition@1 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@2 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@3 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@5 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x0>;
		};
	};

	qspi_nor_cs0: m25p80@0 {
		status = "okay";

		pinctrl-names = "default";
		pinctrl-0 = <&qspi1_cs0_pin>;
		compatible = "n25q128a13", "jedec,spi-nor";

		reg = <0>;
		spi-max-frequency = <76800000>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		#address-cells = <1>;
		#size-cells = <1>;

		/* MTD partition table.
		 * The ROM checks the first four physical blocks
		 * for a valid file to boot and the flash here is
		 * 64KiB block size.
		 */
		partition@0 {
			label = "QSPI.SPL";
			reg = <0x00000000 0x000040000>;
		};
		partition@1 {
			label = "QSPI.u-boot";
			reg = <0x00040000 0x00100000>;
		};
		partition@2 {
			label = "QSPI.u-boot-spl-os";
			reg = <0x00140000 0x00080000>;
		};
		partition@3 {
			label = "QSPI.u-boot-env";
			reg = <0x001c0000 0x00010000>;
		};
		partition@4 {
			label = "QSPI.u-boot-env.backup1";
			reg = <0x001d0000 0x0010000>;
		};
		partition@5 {
			label = "QSPI.kernel";
			reg = <0x001e0000 0x0800000>;
		};
		partition@6 {
			label = "QSPI.file-system";
			reg = <0x009e0000 0x0>;
		};
	};
};

&gpmc {
	status = "disabled";
	pinctrl-names = "default";
	pinctrl-0 = <&gpmc_nand_pins_default>;

	ranges = <0 0 0x08000000 0x01000000>;		/* minimum GPMC partition = 16MB */

	nand@0,0 {
		compatible = "ti,omap2-nand";
		reg = <0 0 4>;				/* device IO registers */
		interrupt-parent = <&gpmc>;
		interrupts = <0 IRQ_TYPE_NONE>,		/* fifoevent */
			<1 IRQ_TYPE_NONE>;		/* termcount */
		rb-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>;	/* gpmc_wait0 pin */

		/* Settings for Micron MT29F8G08ABACAWP 1GB NAND */
		ti,nand-ecc-opt = "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <35>;
		gpmc,cs-wr-off-ns = <25>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <35>;
		gpmc,adv-wr-off-ns = <25>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <15>;
		gpmc,oe-on-ns = <15>;
		gpmc,oe-off-ns = <30>;
		gpmc,access-ns = <35>;
		gpmc,wr-access-ns = <25>;
		gpmc,rd-cycle-ns = <35>;
		gpmc,wr-cycle-ns = <25>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wr-data-mux-bus-ns = <0>;

		/* MTD partition table for 1GB NAND */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x000C0000 0x00040000>;
		};
		partition@4 {
			label = "NAND.u-boot";
			reg = <0x00100000 0x00200000>;
		};
		partition@5 {
			label = "NAND.u-boot-env";
			reg = <0x00300000 0x00040000>;
		};
		partition@6 {
			label = "NAND.file-system";
			reg = <0x00340000 0>;
		};
	};
};

&mailbox3 {
	status = "okay";
	mbox_pru1_0: mbox_pru1_0 {
		status = "okay";
	};
	mbox_pru1_1: mbox_pru1_1 {
		status = "okay";
	};
};

&mailbox4 {
	status = "okay";
	mbox_pru2_0: mbox_pru2_0 {
		status = "okay";
	};
	mbox_pru2_1: mbox_pru2_1 {
		status = "okay";
	};
};

&ipu1 {
	status = "okay";
	memory-region = <&ipu1_memory_region>;
};

&ipu2 {
	status = "okay";
	memory-region = <&ipu2_memory_region>;
};

&dsp1 {
	status = "okay";
	memory-region = <&dsp1_memory_region>;
};

&pruss1 {
	status = "okay";
};

&pru1_0 {
	mboxes = <&mailbox3 &mbox_pru1_0>;
	status = "okay";
};

&pru1_1 {
	mboxes = <&mailbox3 &mbox_pru1_1>;
	status = "okay";
};

&pruss2 {
	status = "okay";
};

&pru2_0 {
	mboxes = <&mailbox4 &mbox_pru2_0>;
	status = "okay";
};

&pru2_1 {
	mboxes = <&mailbox4 &mbox_pru2_1>;
	status = "okay";
};

&pcie2_ep {
	status = "okay";
};

&axi1 {
	status = "okay";
};

&rtc {
	status = "okay";
};