OMAPCONF (rev v1.73-19-gbe8626b built Tue Nov 27 22:27:21 UTC 2018) HW Platform: Generic DRA74X (Flattened Device Tree) DRA76X ES1.0 GP Device (STANDARD performance (1.8GHz)) UNKNOWN POWER IC SW Build Details: Build: Version: UNKNOWN Kernel: Version: 4.4.84-SMS_MONOLYTHIC-svn53 Author: tdax@avo-VirtualBox Toolchain: gcc version 4.7.3 (Ubuntu/Linaro 4.7.3-12ubuntu1) Type: #44 SMP PREEMPT Date: Fri Nov 23 08:28:15 CET 2018 ************************************************** ****** Decoding AMMU Mappings for IPU1 ****** ************************************************** *** Decoding Large Page 0 *** CACHE_MMU_LARGE_ADDR_0 = 0x40000000 CACHE_MMU_LARGE_XLTE_0 = 0x40000000 CACHE_MMU_LARGE_POLICY_0 = 0x00000003 PAGE ENABLED Logical Address = 0x40000000 - 0x5FFFFFFF Physical address = 0x40000000 - 0x5FFFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 512 MB page *** Decoding Large Page 1 *** CACHE_MMU_LARGE_ADDR_1 = 0x90000000 CACHE_MMU_LARGE_XLTE_1 = 0x90000000 CACHE_MMU_LARGE_POLICY_1 = 0x000B0001 PAGE ENABLED Logical Address = 0x90000000 - 0x91FFFFFF Physical address = 0x90000000 - 0x91FFFFFF Policy * L1 write policy is writeback * L1 allocate policy: no writes allocated * L1 writes posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 32 MB page *** Decoding Large Page 2 *** CACHE_MMU_LARGE_ADDR_2 = 0xC0000000 CACHE_MMU_LARGE_XLTE_2 = 0xC0000000 CACHE_MMU_LARGE_POLICY_2 = 0x00000003 PAGE ENABLED Logical Address = 0xC0000000 - 0xDFFFFFFF Physical address = 0xC0000000 - 0xDFFFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 512 MB page *** Decoding Large Page 3 *** CACHE_MMU_LARGE_ADDR_3 = 0x92000000 CACHE_MMU_LARGE_XLTE_3 = 0x92000000 CACHE_MMU_LARGE_POLICY_3 = 0x00000001 PAGE ENABLED Logical Address = 0x92000000 - 0x93FFFFFF Physical address = 0x92000000 - 0x93FFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 32 MB page *** Decoding Medium Page 0 *** CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000 CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000 CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003 PAGE ENABLED Logical Address = 0x63300000 - 0x6333FFFF Physical address = 0x43300000 - 0x4333FFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 256 KB page *** Decoding Medium Page 1 *** CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000 CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000 CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003 PAGE ENABLED Logical Address = 0x63400000 - 0x6343FFFF Physical address = 0x43400000 - 0x4343FFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 256 KB page *** Decoding Small Page 0 *** CACHE_MMU_SMALL_ADDR_0 = 0x00000000 CACHE_MMU_SMALL_XLTE_0 = 0x55020000 CACHE_MMU_SMALL_POLICY_0 = 0x0001000B PAGE ENABLED Logical Address = 0x00000000 - 0x00003FFF Physical address = 0x55020000 - 0x55023FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 1 *** CACHE_MMU_SMALL_ADDR_1 = 0x40000000 CACHE_MMU_SMALL_XLTE_1 = 0x55080000 CACHE_MMU_SMALL_POLICY_1 = 0x0000000B PAGE ENABLED Logical Address = 0x40000000 - 0x40003FFF Physical address = 0x55080000 - 0x55083FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 2 *** CACHE_MMU_SMALL_ADDR_2 = 0x00004000 CACHE_MMU_SMALL_XLTE_2 = 0x55024000 CACHE_MMU_SMALL_POLICY_2 = 0x0001000B PAGE ENABLED Logical Address = 0x00004000 - 0x00007FFF Physical address = 0x55024000 - 0x55027FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 3 *** CACHE_MMU_SMALL_ADDR_3 = 0x00008000 CACHE_MMU_SMALL_XLTE_3 = 0x55028000 CACHE_MMU_SMALL_POLICY_3 = 0x0001000B PAGE ENABLED Logical Address = 0x00008000 - 0x0000BFFF Physical address = 0x55028000 - 0x5502BFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 4 *** CACHE_MMU_SMALL_ADDR_4 = 0x00000000 CACHE_MMU_SMALL_XLTE_4 = 0x00000000 CACHE_MMU_SMALL_POLICY_4 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 5 *** CACHE_MMU_SMALL_ADDR_5 = 0x00000000 CACHE_MMU_SMALL_XLTE_5 = 0x00000000 CACHE_MMU_SMALL_POLICY_5 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 6 *** CACHE_MMU_SMALL_ADDR_6 = 0x00000000 CACHE_MMU_SMALL_XLTE_6 = 0x00000000 CACHE_MMU_SMALL_POLICY_6 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 7 *** CACHE_MMU_SMALL_ADDR_7 = 0x00000000 CACHE_MMU_SMALL_XLTE_7 = 0x00000000 CACHE_MMU_SMALL_POLICY_7 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 8 *** CACHE_MMU_SMALL_ADDR_8 = 0x00000000 CACHE_MMU_SMALL_XLTE_8 = 0x00000000 CACHE_MMU_SMALL_POLICY_8 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 9 *** CACHE_MMU_SMALL_ADDR_9 = 0x00000000 CACHE_MMU_SMALL_XLTE_9 = 0x00000000 CACHE_MMU_SMALL_POLICY_9 = 0x00000000 PAGE NOT ENABLED ************************************************** ****** Decoding AMMU Mappings for IPU2 ****** ************************************************** *** Decoding Large Page 0 *** CACHE_MMU_LARGE_ADDR_0 = 0x40000000 CACHE_MMU_LARGE_XLTE_0 = 0x40000000 CACHE_MMU_LARGE_POLICY_0 = 0x00000003 PAGE ENABLED Logical Address = 0x40000000 - 0x5FFFFFFF Physical address = 0x40000000 - 0x5FFFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 512 MB page *** Decoding Large Page 1 *** CACHE_MMU_LARGE_ADDR_1 = 0x92000000 CACHE_MMU_LARGE_XLTE_1 = 0x92000000 CACHE_MMU_LARGE_POLICY_1 = 0x000B0001 PAGE ENABLED Logical Address = 0x92000000 - 0x93FFFFFF Physical address = 0x92000000 - 0x93FFFFFF Policy * L1 write policy is writeback * L1 allocate policy: no writes allocated * L1 writes posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 32 MB page *** Decoding Large Page 2 *** CACHE_MMU_LARGE_ADDR_2 = 0xC0000000 CACHE_MMU_LARGE_XLTE_2 = 0xC0000000 CACHE_MMU_LARGE_POLICY_2 = 0x00000003 PAGE ENABLED Logical Address = 0xC0000000 - 0xDFFFFFFF Physical address = 0xC0000000 - 0xDFFFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 512 MB page *** Decoding Large Page 3 *** CACHE_MMU_LARGE_ADDR_3 = 0x00000000 CACHE_MMU_LARGE_XLTE_3 = 0x00000000 CACHE_MMU_LARGE_POLICY_3 = 0x00000000 PAGE NOT ENABLED *** Decoding Medium Page 0 *** CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000 CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000 CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003 PAGE ENABLED Logical Address = 0x63300000 - 0x6333FFFF Physical address = 0x43300000 - 0x4333FFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 256 KB page *** Decoding Medium Page 1 *** CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000 CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000 CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003 PAGE ENABLED Logical Address = 0x63400000 - 0x6343FFFF Physical address = 0x43400000 - 0x4343FFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 256 KB page *** Decoding Small Page 0 *** CACHE_MMU_SMALL_ADDR_0 = 0x00000000 CACHE_MMU_SMALL_XLTE_0 = 0x55020000 CACHE_MMU_SMALL_POLICY_0 = 0x0001000B PAGE ENABLED Logical Address = 0x00000000 - 0x00003FFF Physical address = 0x55020000 - 0x55023FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 1 *** CACHE_MMU_SMALL_ADDR_1 = 0x40000000 CACHE_MMU_SMALL_XLTE_1 = 0x55080000 CACHE_MMU_SMALL_POLICY_1 = 0x0000000B PAGE ENABLED Logical Address = 0x40000000 - 0x40003FFF Physical address = 0x55080000 - 0x55083FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 2 *** CACHE_MMU_SMALL_ADDR_2 = 0x00004000 CACHE_MMU_SMALL_XLTE_2 = 0x55024000 CACHE_MMU_SMALL_POLICY_2 = 0x0001000B PAGE ENABLED Logical Address = 0x00004000 - 0x00007FFF Physical address = 0x55024000 - 0x55027FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 3 *** CACHE_MMU_SMALL_ADDR_3 = 0x00008000 CACHE_MMU_SMALL_XLTE_3 = 0x55028000 CACHE_MMU_SMALL_POLICY_3 = 0x0001000B PAGE ENABLED Logical Address = 0x00008000 - 0x0000BFFF Physical address = 0x55028000 - 0x5502BFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 4 *** CACHE_MMU_SMALL_ADDR_4 = 0x00000000 CACHE_MMU_SMALL_XLTE_4 = 0x00000000 CACHE_MMU_SMALL_POLICY_4 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 5 *** CACHE_MMU_SMALL_ADDR_5 = 0x00000000 CACHE_MMU_SMALL_XLTE_5 = 0x00000000 CACHE_MMU_SMALL_POLICY_5 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 6 *** CACHE_MMU_SMALL_ADDR_6 = 0x00000000 CACHE_MMU_SMALL_XLTE_6 = 0x00000000 CACHE_MMU_SMALL_POLICY_6 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 7 *** CACHE_MMU_SMALL_ADDR_7 = 0x00000000 CACHE_MMU_SMALL_XLTE_7 = 0x00000000 CACHE_MMU_SMALL_POLICY_7 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 8 *** CACHE_MMU_SMALL_ADDR_8 = 0x00000000 CACHE_MMU_SMALL_XLTE_8 = 0x00000000 CACHE_MMU_SMALL_POLICY_8 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 9 *** CACHE_MMU_SMALL_ADDR_9 = 0x00000000 CACHE_MMU_SMALL_XLTE_9 = 0x00000000 CACHE_MMU_SMALL_POLICY_9 = 0x00000000 PAGE NOT ENABLED *** Decoding Large Page 0 *** CACHE_MMU_LARGE_ADDR_0 = 0x40000000 CACHE_MMU_LARGE_XLTE_0 = 0x40000000 CACHE_MMU_LARGE_POLICY_0 = 0x00000003 PAGE ENABLED Logical Address = 0x40000000 - 0x5FFFFFFF Physical address = 0x40000000 - 0x5FFFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 512 MB page *** Decoding Large Page 1 *** CACHE_MMU_LARGE_ADDR_1 = 0x90000000 CACHE_MMU_LARGE_XLTE_1 = 0x90000000 CACHE_MMU_LARGE_POLICY_1 = 0x000B0001 PAGE ENABLED Logical Address = 0x90000000 - 0x91FFFFFF Physical address = 0x90000000 - 0x91FFFFFF Policy * L1 write policy is writeback * L1 allocate policy: no writes allocated * L1 writes posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 32 MB page *** Decoding Large Page 2 *** CACHE_MMU_LARGE_ADDR_2 = 0xC0000000 CACHE_MMU_LARGE_XLTE_2 = 0xC0000000 CACHE_MMU_LARGE_POLICY_2 = 0x00000003 PAGE ENABLED Logical Address = 0xC0000000 - 0xDFFFFFFF Physical address = 0xC0000000 - 0xDFFFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 512 MB page *** Decoding Large Page 3 *** CACHE_MMU_LARGE_ADDR_3 = 0x92000000 CACHE_MMU_LARGE_XLTE_3 = 0x92000000 CACHE_MMU_LARGE_POLICY_3 = 0x00000001 PAGE ENABLED Logical Address = 0x92000000 - 0x93FFFFFF Physical address = 0x92000000 - 0x93FFFFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 32 MB page *** Decoding Medium Page 0 *** CACHE_MMU_MEDIUM_ADDR_0 = 0x63300000 CACHE_MMU_MEDIUM_XLTE_0 = 0x43300000 CACHE_MMU_MEDIUM_POLICY_0 = 0x00000003 PAGE ENABLED Logical Address = 0x63300000 - 0x6333FFFF Physical address = 0x43300000 - 0x4333FFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 256 KB page *** Decoding Medium Page 1 *** CACHE_MMU_MEDIUM_ADDR_1 = 0x63400000 CACHE_MMU_MEDIUM_XLTE_1 = 0x43400000 CACHE_MMU_MEDIUM_POLICY_1 = 0x00000003 PAGE ENABLED Logical Address = 0x63400000 - 0x6343FFFF Physical address = 0x43400000 - 0x4343FFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Do not follow volatile qualifier * 256 KB page *** Decoding Small Page 0 *** CACHE_MMU_SMALL_ADDR_0 = 0x00000000 CACHE_MMU_SMALL_XLTE_0 = 0x55020000 CACHE_MMU_SMALL_POLICY_0 = 0x0001000B PAGE ENABLED Logical Address = 0x00000000 - 0x00003FFF Physical address = 0x55020000 - 0x55023FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 1 *** CACHE_MMU_SMALL_ADDR_1 = 0x40000000 CACHE_MMU_SMALL_XLTE_1 = 0x55080000 CACHE_MMU_SMALL_POLICY_1 = 0x0000000B PAGE ENABLED Logical Address = 0x40000000 - 0x40003FFF Physical address = 0x55080000 - 0x55083FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 noncacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 2 *** CACHE_MMU_SMALL_ADDR_2 = 0x00004000 CACHE_MMU_SMALL_XLTE_2 = 0x55024000 CACHE_MMU_SMALL_POLICY_2 = 0x0001000B PAGE ENABLED Logical Address = 0x00004000 - 0x00007FFF Physical address = 0x55024000 - 0x55027FFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 3 *** CACHE_MMU_SMALL_ADDR_3 = 0x00008000 CACHE_MMU_SMALL_XLTE_3 = 0x55028000 CACHE_MMU_SMALL_POLICY_3 = 0x0001000B PAGE ENABLED Logical Address = 0x00008000 - 0x0000BFFF Physical address = 0x55028000 - 0x5502BFFF Policy * L1 write policy is writethrough * L1 allocate policy: no writes allocated * L1 writes non-posted * L1 cacheable * Do not send cache exclusion sideband * Preload disabled * Read/Write * Read/Write/Execute * Follow volatile qualifier * 16 KB page *** Decoding Small Page 4 *** CACHE_MMU_SMALL_ADDR_4 = 0x00000000 CACHE_MMU_SMALL_XLTE_4 = 0x00000000 CACHE_MMU_SMALL_POLICY_4 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 5 *** CACHE_MMU_SMALL_ADDR_5 = 0x00000000 CACHE_MMU_SMALL_XLTE_5 = 0x00000000 CACHE_MMU_SMALL_POLICY_5 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 6 *** CACHE_MMU_SMALL_ADDR_6 = 0x00000000 CACHE_MMU_SMALL_XLTE_6 = 0x00000000 CACHE_MMU_SMALL_POLICY_6 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 7 *** CACHE_MMU_SMALL_ADDR_7 = 0x00000000 CACHE_MMU_SMALL_XLTE_7 = 0x00000000 CACHE_MMU_SMALL_POLICY_7 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 8 *** CACHE_MMU_SMALL_ADDR_8 = 0x00000000 CACHE_MMU_SMALL_XLTE_8 = 0x00000000 CACHE_MMU_SMALL_POLICY_8 = 0x00000000 PAGE NOT ENABLED *** Decoding Small Page 9 *** CACHE_MMU_SMALL_ADDR_9 = 0x00000000 CACHE_MMU_SMALL_XLTE_9 = 0x00000000 CACHE_MMU_SMALL_POLICY_9 = 0x00000000 PAGE NOT ENABLED